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Title: Cellular array processor with individual cell-level data-dependent cell control and multiport input memory

Abstract

In a processor array of the type including a plurality of individual processing cells, the combination therewith of a processing cell structure for inclusion in the array. The processing cell comprising: memory means having multiple input ports each for receiving separate input data from the controller and a plurality of output ports, an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of the memory means, with the arithmetic logic unit having an output port, first register means coupled to the output port of the ALU for determining the status of the cell and for providing status data, second register means coupled to the first register means and the controller and operative to receive instructions from the controller and status data from the first register means to store therein a code indicative of an operating condition for the cell.

Inventors:
Publication Date:
OSTI Identifier:
6895782
Patent Number(s):
US 4907148; A
Application Number:
PPN: US 7-163177A
Assignee:
Alcatel USA Corp., New York, NY
Resource Type:
Patent
Resource Relation:
Patent File Date: 26 Feb 1988
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ARRAY PROCESSORS; PARALLEL PROCESSING; SUPERCOMPUTERS; COMPUTER ARCHITECTURE; MEMORY DEVICES; COMPUTERS; DIGITAL COMPUTERS; PROGRAMMING; 990200* - Mathematics & Computers

Citation Formats

Morton, S G. Cellular array processor with individual cell-level data-dependent cell control and multiport input memory. United States: N. p., 1990. Web.
Morton, S G. Cellular array processor with individual cell-level data-dependent cell control and multiport input memory. United States.
Morton, S G. Tue . "Cellular array processor with individual cell-level data-dependent cell control and multiport input memory". United States.
@article{osti_6895782,
title = {Cellular array processor with individual cell-level data-dependent cell control and multiport input memory},
author = {Morton, S G},
abstractNote = {In a processor array of the type including a plurality of individual processing cells, the combination therewith of a processing cell structure for inclusion in the array. The processing cell comprising: memory means having multiple input ports each for receiving separate input data from the controller and a plurality of output ports, an arithmetic logic unit (ALU) having a plurality of input ports each separate one coupled to an output port of the memory means, with the arithmetic logic unit having an output port, first register means coupled to the output port of the ALU for determining the status of the cell and for providing status data, second register means coupled to the first register means and the controller and operative to receive instructions from the controller and status data from the first register means to store therein a code indicative of an operating condition for the cell.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1990},
month = {3}
}