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Title: Status of the interlaboratory development of a high-speed standard data bus: FASTBUS

Abstract

The FASTBUS project is an interlaboratory effort to develop a next-generation laboratory standard data bus. The principal design goals are high speed (< 100 ns per word block transfers), wide data path (32 bits), identical parallel addressing architectures at both system and sub-system levels, ability to support multiple parallel master controllers, and ability to support special modes of operation for high-energy physics applications. The current status of development is briefly described. 10 figures, 2 tables.

Authors:
Publication Date:
Research Org.:
Stanford Linear Accelerator Center, CA
OSTI Identifier:
6872381
Alternate Identifier(s):
OSTI ID: 6872381
Resource Type:
Journal Article
Journal Name:
IEEE Trans. Nucl. Sci.; (United States)
Additional Journal Information:
Journal Volume: NS-26:1
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; DATA TRANSMISSION; EQUIPMENT; EQUIPMENT INTERFACES; DESIGN; COMMUNICATIONS 420800* -- Engineering-- Electronic Circuits & Devices-- (-1989)

Citation Formats

Larsen, R.S. Status of the interlaboratory development of a high-speed standard data bus: FASTBUS. United States: N. p., 1979. Web. doi:10.1109/TNS.1979.4329708.
Larsen, R.S. Status of the interlaboratory development of a high-speed standard data bus: FASTBUS. United States. doi:10.1109/TNS.1979.4329708.
Larsen, R.S. Thu . "Status of the interlaboratory development of a high-speed standard data bus: FASTBUS". United States. doi:10.1109/TNS.1979.4329708.
@article{osti_6872381,
title = {Status of the interlaboratory development of a high-speed standard data bus: FASTBUS},
author = {Larsen, R.S.},
abstractNote = {The FASTBUS project is an interlaboratory effort to develop a next-generation laboratory standard data bus. The principal design goals are high speed (< 100 ns per word block transfers), wide data path (32 bits), identical parallel addressing architectures at both system and sub-system levels, ability to support multiple parallel master controllers, and ability to support special modes of operation for high-energy physics applications. The current status of development is briefly described. 10 figures, 2 tables.},
doi = {10.1109/TNS.1979.4329708},
journal = {IEEE Trans. Nucl. Sci.; (United States)},
number = ,
volume = NS-26:1,
place = {United States},
year = {1979},
month = {2}
}