An empirical hierarchical memory model based on hardware performance counters

Conference · Tue Sep 01 00:00:00 EDT 1998

OSTI ID:674716

Lubeck, O M; Luo, Y; Wasserman, H; Bassetti, F

In this paper, the authors characterize application performance with a memory-centric view. Using a simple strategy and performance data measured by on-chip hardware performance counters, they model the performance of a simple memory hierarchy and infer the contribution of each level in the memory system to an application`s overall cycles per instruction (cpi). They account for the overlap of processor execution with memory accesses--a key parameter not directly measurable on most systems. They infer the separate contributions of three major architecture features in the memory subsystem of the Origin 2000: cache size, outstanding loads-under-miss, and memory latency.

• Research Organization: Los Alamos National Lab. (LANL), Los Alamos, NM (United States)
• Sponsoring Organization: USDOE, Washington, DC (United States)
• DOE Contract Number: W-7405-ENG-36
• OSTI ID: 674716
• Report Number(s): LA-UR-98-1130; CONF-980747-; ON: DE98006319; TRN: AHC29820%%171
• Resource Relation: Conference: International conference on parallel and distributed processing techniques and applications, Las Vegas, NV (United States), 13-16 Jul 1998; Other Information: PBD: [1998]
• Country of Publication: United States
• Language: English

Related Subjects

99 MATHEMATICS
COMPUTERS
INFORMATION SCIENCE
MANAGEMENT
LAW
MISCELLANEOUS
PERFORMANCE
MEMORY DEVICES
COMPUTER ARCHITECTURE
MICROPROCESSORS
MEMORY MANAGEMENT