System overview of FASTBUS
FASTBUS is an emerging standard for a high-speed data acquisition bus designed to meet the requirements of the next generation of large-scale physics experiments. It incorporates several powerful features: a 32-bit data address field; high-speed (< 100 ns) 32-bit data transfers; multiple bus segments permitting a high degree of independent and parallel activity; multiple controllers on a single segment; a protocol (uniform system - wide) with asynchronous handshaked operations to accommodate different speed devices reliably, but which also allows synchronous nonhandshaked operations for transferring blocks at maximum speed; the ability to broadcast commands from any point in the system to the whole system or to selected portions of it; and the ability to extract data from large, sparsely populated arrays rapidly. These features are described in detail, and the present state of development of the standard is briefly reviewed. 10 figures, 3 tables.
- Research Organization:
- Massachusetts Inst. of Tech., Cambridge
- OSTI ID:
- 6654399
- Journal Information:
- IEEE Trans. Nucl. Sci.; (United States), Vol. NS-27:1
- Country of Publication:
- United States
- Language:
- English
Similar Records
Introduction to the Fastbus
Introduction to the Fastbus