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Title: Parallel processing system apparatus

Abstract

This patent describes a processing element for use in a single instruction multiple data parallel processing system comprising a processing element. The element consists of: an arithmetic/logic unit (ALU) comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate coupled to receive a first input signal and apply an output signal to the ALU; memory means for storing a signal, the signal stored in the memory means being outputted to the gate; and the gate providing the output signal to the ALU as the complement of the first input signal only upon a second being stored in the memory means and thereby outputted to the gate, the gate providing the output signal to the ALU as the first input signal in the absence of the second signal.

Inventors:
;
Publication Date:
OSTI Identifier:
6600983
Patent Number(s):
US 4775952
Assignee:
General Electric Co., Schenectady, NY
Resource Type:
Patent
Resource Relation:
Patent File Date: Filed date 29 May 1986
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; SUPERCOMPUTERS; PARALLEL PROCESSING; ARRAY PROCESSORS; COMPUTER ARCHITECTURE; GATING CIRCUITS; LOGIC CIRCUITS; MEMORY DEVICES; SIGNAL CONDITIONING; COMPUTERS; DIGITAL COMPUTERS; ELECTRONIC CIRCUITS; PROGRAMMING; 990210* - Supercomputers- (1987-1989)

Citation Formats

Danielsson, P E, and Mattheyses, R M. Parallel processing system apparatus. United States: N. p., 1988. Web.
Danielsson, P E, & Mattheyses, R M. Parallel processing system apparatus. United States.
Danielsson, P E, and Mattheyses, R M. Tue . "Parallel processing system apparatus". United States.
@article{osti_6600983,
title = {Parallel processing system apparatus},
author = {Danielsson, P E and Mattheyses, R M},
abstractNote = {This patent describes a processing element for use in a single instruction multiple data parallel processing system comprising a processing element. The element consists of: an arithmetic/logic unit (ALU) comprising electronic circuitry for performing binary logic operations on signals applied thereto; an exclusive-OR gate coupled to receive a first input signal and apply an output signal to the ALU; memory means for storing a signal, the signal stored in the memory means being outputted to the gate; and the gate providing the output signal to the ALU as the complement of the first input signal only upon a second being stored in the memory means and thereby outputted to the gate, the gate providing the output signal to the ALU as the first input signal in the absence of the second signal.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1988},
month = {10}
}