Switching speed of DCLgates with highJ /SUB c/ Josephson junctions
Abstract
Switching speed and bias current margin of DCLgates composed of highJ /SUB c/ junctions are investigated by both numerical calculation and experimental measurement. It is shown that switching speed is improved by increasing J /SUB c/ . However, the switching speed and bias current margin of DCLgates are restricted by the increase in the minimum resetting current for the highJ /SUB c/ junction. The theoretical J /SUB c/ limit for a Nb oxide barrier junction is found to be about 7 X 10/sup 8/ A/m/sup 2/ from numerical results, and the J /SUB c/ values that produce bias current margins of greater than 20 % are found by both numerical and experimental results to be less than 2 about 3 X 10/sup 8/ A/m/sup 2/. The switching delay obtained experimentally for a DCLgate with a J /SUB c/ value of 2 X 10/sup 8/ A/m/sup 2/ is 5.6 ps, which is in good agreement with the numerical result.
 Authors:
 Publication Date:
 Research Org.:
 Central Research Laboratory, Hitachi, Ltd., Kokubunji 185, Tokyo
 OSTI Identifier:
 6485609
 Alternate Identifier(s):
 OSTI ID: 6485609
 Report Number(s):
 CONF840937
Journal ID: CODEN: IEMGA
 Resource Type:
 Conference
 Resource Relation:
 Journal Name: IEEE Trans. Magn.; (United States); Journal Volume: MAG21:2; Conference: Applied superconductivity conference, San Diego, CA, USA, 9 Sep 1984
 Country of Publication:
 United States
 Language:
 English
 Subject:
 71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; GATING CIRCUITS; PERFORMANCE; TIMING PROPERTIES; LOGIC CIRCUITS; JOSEPHSON JUNCTIONS; SWITCHING CIRCUITS; ELECTRONIC CIRCUITS; JUNCTIONS; SUPERCONDUCTING JUNCTIONS 420201*  Engineering Cryogenic Equipment & Devices
Citation Formats
Nishino, T., Hatano, Y., Kawabe, U., and Tarutani, Y. Switching speed of DCLgates with highJ /SUB c/ Josephson junctions. United States: N. p., 1985.
Web.
Nishino, T., Hatano, Y., Kawabe, U., & Tarutani, Y. Switching speed of DCLgates with highJ /SUB c/ Josephson junctions. United States.
Nishino, T., Hatano, Y., Kawabe, U., and Tarutani, Y. Fri .
"Switching speed of DCLgates with highJ /SUB c/ Josephson junctions". United States.
doi:.
@article{osti_6485609,
title = {Switching speed of DCLgates with highJ /SUB c/ Josephson junctions},
author = {Nishino, T. and Hatano, Y. and Kawabe, U. and Tarutani, Y.},
abstractNote = {Switching speed and bias current margin of DCLgates composed of highJ /SUB c/ junctions are investigated by both numerical calculation and experimental measurement. It is shown that switching speed is improved by increasing J /SUB c/ . However, the switching speed and bias current margin of DCLgates are restricted by the increase in the minimum resetting current for the highJ /SUB c/ junction. The theoretical J /SUB c/ limit for a Nb oxide barrier junction is found to be about 7 X 10/sup 8/ A/m/sup 2/ from numerical results, and the J /SUB c/ values that produce bias current margins of greater than 20 % are found by both numerical and experimental results to be less than 2 about 3 X 10/sup 8/ A/m/sup 2/. The switching delay obtained experimentally for a DCLgate with a J /SUB c/ value of 2 X 10/sup 8/ A/m/sup 2/ is 5.6 ps, which is in good agreement with the numerical result.},
doi = {},
journal = {IEEE Trans. Magn.; (United States)},
number = ,
volume = MAG21:2,
place = {United States},
year = {Fri Mar 01 00:00:00 EST 1985},
month = {Fri Mar 01 00:00:00 EST 1985}
}

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