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Title: List processing software for the LeCroy 1821 Segment Manager Interface

Abstract

Many experiments at Fermilab now include some FASTBUS electronics in their data readout. The software reported in this paper provides general support for the LeCroy 1821 interface. The list processing device drivers allow FASTBUS data to be read out efficiently into the Fermilab Computing Department supported data acquisition systems.

Authors:
; ;
Publication Date:
Research Org.:
Fermi National Accelerator Lab., Batavia, IL (USA)
OSTI Identifier:
6314302
Report Number(s):
FNAL-TM-1458; CONF-870552-18
ON: DE87011000
DOE Contract Number:
AC02-76CH03000
Resource Type:
Conference
Resource Relation:
Conference: 5. conference on real-time computer applications in nuclear, particle, and plasma physics, San Francisco, CA, USA, 12 May 1987; Other Information: Paper copy only, copy does not permit microfiche production. Original copy available until stock is exhausted
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; DATA ACQUISITION SYSTEMS; COMPUTER CODES; INTERFACES; DEC COMPUTERS; FASTBUS SYSTEM; COMPUTERS; 990220* - Computers, Computerized Models, & Computer Programs- (1987-1989)

Citation Formats

Dorries, T., Moore, C., and Pordes, R. List processing software for the LeCroy 1821 Segment Manager Interface. United States: N. p., 1987. Web.
Dorries, T., Moore, C., & Pordes, R. List processing software for the LeCroy 1821 Segment Manager Interface. United States.
Dorries, T., Moore, C., and Pordes, R. 1987. "List processing software for the LeCroy 1821 Segment Manager Interface". United States. doi:. https://www.osti.gov/servlets/purl/6314302.
@article{osti_6314302,
title = {List processing software for the LeCroy 1821 Segment Manager Interface},
author = {Dorries, T. and Moore, C. and Pordes, R.},
abstractNote = {Many experiments at Fermilab now include some FASTBUS electronics in their data readout. The software reported in this paper provides general support for the LeCroy 1821 interface. The list processing device drivers allow FASTBUS data to be read out efficiently into the Fermilab Computing Department supported data acquisition systems.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = 1987,
month = 5
}

Conference:
Other availability
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  • Many fixed target experiments at Fermilab now include some FASTBUS electronics in their data readout. The software reported in this paper, provides general support for the LeCroy 1821 interface. The list processing device drivers allow FASTBUS data to be read out efficiently into the Fermilab Computing Department supported data acquisition systems.
  • An interface between multiple LeCroy Segment Managers and a VME-VMX system is described. The host I/O registers of the 1821, and control registers for DMA have been mapped into the short I/O address space of VME. Transfers from the data memory of the 1821 occur via pipelined DMA to the VMXbus. As many as sixteen Segment Managers may be controlled by a single interface.
  • An interface between multiple LeCroy Segment Managers and a VME-VMX system is described. The host I/O registers of the 1821, and control registers for DMA have been mapped into the short I/O address space of VME. Transfers from the data memory of the 1821 occur via pipelined DMA to the VMXbus. As many as sixteen Segment Managers may be controlled by a single interface.
  • A programmable analog memory address list manager/controller has been developed for use with all analog memory-based detector subsystems of PHENIX. The unit provides simultaneous read/write control, cell write-over protection for both a Level-1 trigger decision delay and digitization latency, and re-ordering of AMU addresses following conversion, at a beam crossing rate of 112 ns. Addresses are handled such that up to 5 Level-1 events can be maintained in the AMU without write-over. Data tagging is implemented for handling overlapping and shared beam event data packets. Full usage in all PHENIX analog memory-based detector sub-systems is accomplished by the use ofmore » detector-specific programmable parameters -- the number of data samples per Level-1 trigger valid and the swnple spacing. Architectural candidates for the system are discussed with emphasis on implementation implications. Details of the design are presented including design simulations, timing information, and test results from a full implementation using programmable logic devices.« less