IEEE P1596, a scalable coherent interface for GigaByte/sec multiprocessor applications
IEEE P159, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained during the development of Fastbus (IEEE 960), Futurebus (IEEE 896.1) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor, efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters and general switched interconnections like Banyan, Omega, or full crossbar networks. To achieve these ambitious goals, SCI must sacrifice the immediate handshake characteristic of the present generation of buses in favor of a packet-like split-cycle protocol. Wire-ORs, broadcasts, and even ordinary passive bus structures are to be avoided. However, a lower performance (1 GByte/sec per backplane instead of per processor) implementation using a register insertion ring architecture on a passive backplane appears to be possible using the same interface as for the more costly switch networks. This paper presents a summary of current directions, and reports the status of the work in progress.
- Research Organization:
- Stanford Linear Accelerator Center, Stanford, CA (US)
- OSTI ID:
- 6264969
- Report Number(s):
- CONF-881103-
- Journal Information:
- IEEE Trans. Nucl. Sci.; (United States), Vol. 36:1; Conference: IEEE nuclear science symposium, Orlando, FL, USA, 9 Nov 1988
- Country of Publication:
- United States
- Language:
- English
Similar Records
Scalable coherent interface
The scalable coherent interface, IEEE P1596; Status and possible applications to data acquisition and physics