Process architectures using MeV implanted blanket buried layers for latch-up improvements on bulk silicon
- Eaton Corporation, Beverly, MA (United States)
- Silicon Engineering, Austin, TX (United States)
Doped buried layers formed by MeV ion implantation are attractive alternatives to expensive epitaxial substrates for controlling latch-up in CMOS devices. Two different process architecture approaches for forming effective buried layers are discussed. P+ Around Boundary (PAB), and a more recent derivative, BILLI are compared to a Buried Layer/Connecting Layer (BUCL) architecture, with regards to latch-up resistance, process flexibility, and future scalability. While both architectures have been shown to increase latch-up trigger current on bulk silicon, the BUCL process provides greater latch-up control and process/device flexibility. Process and device simulations as well as experimental data indicate that a properly chosen set of implants for both n-well, p-well, and buried layer structures can yield latch-up isolation superior to 3mm epi.
- OSTI ID:
- 621260
- Report Number(s):
- CONF-9606110-; TRN: 98:002114-0003
- Resource Relation:
- Conference: 11. international conference on ion implantation technology, Austin, TX (United States), 17-21 Jun 1996; Other Information: PBD: 1996; Related Information: Is Part Of Ion implantation technology - 96; Ishida, E.; Banerjee, S.; Mehta, S. [eds.] [and others]; PB: 859 p.
- Country of Publication:
- United States
- Language:
- English
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