Interleaved pipeline parallel processing architecture
This patent describes a system for processing of data. The data being inputted in a serial pipeline in a predetermined order into the system such that a second packet of data is inputted into the system before a first packet of data, the system comprising: a system input in the serial pipeline: a system output in the serial pipeline; a first processor in the serial pipeline coupled to the system input for receiving the first and the second packets of data, the first processor receiving the second packet of data and passing the second packet of data to a second processor in the serial pipeline coupled to the first processor, the first processor receiving the first packet of data and performing a computational operation on the first packet of data. The first processor outputting the result of its operation on the first packet of data to the second processor, the first processor having a first means for assuring that the first processor operates on only the first packet of data and a means for assuring that the second packet of data is passed to the second processor before the result of the operation on the first packet of data is outputted to the second processor. The second processor coupled to the system output, the second processor receiving the second packet of data and performing a computational operation on the second packet of data, the second processor outputting to the system output the result of its operation on the second packet of data, the second processor receiving the result of the operation of the first processor on the first packet of data, the second processor passing the result of the operation of the first processor on the first packet of data to the system output.
- Assignee:
- Silicon Graphics, Inc., Mountain View, CA
- Patent Number(s):
- US 4789927
- OSTI ID:
- 6201341
- Resource Relation:
- Patent File Date: Filed date 7 Apr 1986
- Country of Publication:
- United States
- Language:
- English
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