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Title: A Josephson-junction analog-to-digital converter with multi-gigahertz bandwidth

Miscellaneous ·
OSTI ID:6184226

The design of a high-speed Josephson junction analog-to-digital (A/D) converter is presented. The A/D converter employs a parallel bank of latching comparator circuits and a binary encoder circuit. The parallel architecture is used to maximize the analog frequency response of the converter. In order to extend the dynamic range of individual comparators, an analog range-limiting circuit is described which uses a Josephson junction with suppressed critical current as the limiting element. Speed measurements performed on fabricated comparators that employ the limiter indicate that 2.7 effective bits of resolution can be achieved at an analog input frequency of 4.8 GHz. Measured logic margins for a four-bit binary encoder show that multiple-input SQUID gates can be successfully utilized to perform the exclusive-OR operation. Design techniques are presented for a multi-layer thin-film Pb-alloy Josephson junction circuit process. The process is described from the design perspective, and details pertaining to thin-film circuit elements are given. High-speed measurements were performed using the Josephson sampling oscilloscope technique. This technique allows high speed transient events on a chip to be measured by placing a Josephson sampling oscilloscope circuit on the chip with the circuit being tested. In this way, measurements do not suffer from losses involved in transmitting signals off-chip. A standardized sampling circuit is shown that allows measurement of a large variety of transient on-chip phenomenon. This sampling circuit is used for a variety of measurements on components of the A/D converter. A cryogenic probe for testing high-speed Josephson circuitry is presented.

Research Organization:
California Univ., Berkeley, CA (USA)
OSTI ID:
6184226
Resource Relation:
Other Information: Thesis (Ph.D)
Country of Publication:
United States
Language:
English