Extending memory hierarchy into multiprocessor interconnection networks
The speed with which processors can access memory is critical to the performance of scaleable, shared-memory parallel computers. An important factor in the effective memory access time is the interconnection network that connects processors and memories. This dissertation proposes and analyzes a novel interconnection network in which data are stored at each switch of the network and may change location dynamically in response to the processors' request patterns. By allowing dynamic routing capabilities and by putting memory into each switch element we create a hybrid network offering the best features of uniform and non-uniform memory distance architectures. In contrast to uniform distance networks, locality of reference can be exploited by placing a data item near the processors currently referencing it. In contrast to static mapping of data onto non-uniform distance networks, the dynamic movement mechanism allows the system to accommodate efficiently software that exhibits phases with differing reference patterns or for which the reference pattern may depend heavily on the data. Finally, in contrast to multiple-copy caching schemes, there is only a single copy of any data item in the system, and so there is no need for coherency protocols.
- Research Organization:
- Washington Univ., Seattle, WA (USA)
- OSTI ID:
- 6088595
- Resource Relation:
- Other Information: Thesis (Ph. D.)
- Country of Publication:
- United States
- Language:
- English
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