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Title: A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter integrated circuit

Abstract

A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter has been designed and tested. The circuit converts 16 channels in parallel via a single slope ramp and Gray code counter algorithm. When biased for 10.0 us conversions of a 2 V input range into 4,050 voltage bins, and ohmically connected to a computer, initial testing shows typical performance is a noise level of 0.3 bis rms, integral non-linearity of 4 bins, adjacent channel crosstalk effects less than 1 bin, and total chip power consumption of 110 mW. The chip contains 16 sample and hold circuits, out of range logic, a Gray-to-binary converter, and tri-state data outputs for microprocessor compatibility. The die size is 4.4 by 1.5 mm in a 2 polysilicon, 1.2 micron feature size CMOS process, and has 52 bonding pads. Off Chip requirements are a single power supply, a single high speed clock, a precision voltage reference, three biasing resistors, and supply filtering capacitors. This custom circuit has advantages of lower power dissipation and less PC board area than competitive approaches, and is designed for further monolithic system integration. Design details and test results are presented.

Authors:
;  [1]
  1. Lawrence Berkeley Lab., CA (United States)
Publication Date:
OSTI Identifier:
5869354
Report Number(s):
CONF-921005-
Journal ID: ISSN 0018-9499; CODEN: IETNAE
DOE Contract Number:  
AC03-76SF00098
Resource Type:
Conference
Journal Name:
IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)
Additional Journal Information:
Journal Volume: 40:4 part 1; Conference: Institute of Electrical and Electronic Engineers (IEEE) nuclear science symposium and medical imaging conference, Orlando, FL (United States), 25-31 Oct 1992; Journal ID: ISSN 0018-9499
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; ANALOG-TO-DIGITAL CONVERTERS; DESIGN; PERFORMANCE; ALGORITHMS; EXPERIMENTAL DATA; INTEGRATED CIRCUITS; PERFORMANCE TESTING; POWER LOSSES; DATA; ELECTRONIC CIRCUITS; ELECTRONIC EQUIPMENT; ENERGY LOSSES; EQUIPMENT; INFORMATION; LOSSES; MATHEMATICAL LOGIC; MICROELECTRONIC CIRCUITS; NUMERICAL DATA; TESTING; 426000* - Engineering- Components, Electron Devices & Circuits- (1990-)

Citation Formats

Milgrome, O B, and Kleinfelder, S A. A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter integrated circuit. United States: N. p., 1993. Web.
Milgrome, O B, & Kleinfelder, S A. A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter integrated circuit. United States.
Milgrome, O B, and Kleinfelder, S A. Sun . "A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter integrated circuit". United States.
@article{osti_5869354,
title = {A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter integrated circuit},
author = {Milgrome, O B and Kleinfelder, S A},
abstractNote = {A monolithic CMOS 16 channel, 12 bit, 10 microsecond analog-to-digital converter has been designed and tested. The circuit converts 16 channels in parallel via a single slope ramp and Gray code counter algorithm. When biased for 10.0 us conversions of a 2 V input range into 4,050 voltage bins, and ohmically connected to a computer, initial testing shows typical performance is a noise level of 0.3 bis rms, integral non-linearity of 4 bins, adjacent channel crosstalk effects less than 1 bin, and total chip power consumption of 110 mW. The chip contains 16 sample and hold circuits, out of range logic, a Gray-to-binary converter, and tri-state data outputs for microprocessor compatibility. The die size is 4.4 by 1.5 mm in a 2 polysilicon, 1.2 micron feature size CMOS process, and has 52 bonding pads. Off Chip requirements are a single power supply, a single high speed clock, a precision voltage reference, three biasing resistors, and supply filtering capacitors. This custom circuit has advantages of lower power dissipation and less PC board area than competitive approaches, and is designed for further monolithic system integration. Design details and test results are presented.},
doi = {},
journal = {IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States)},
issn = {0018-9499},
number = ,
volume = 40:4 part 1,
place = {United States},
year = {1993},
month = {8}
}

Conference:
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