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Title: Message-passing multiprocessor simulator

Abstract

The structure and use of a message-passing multiprocessor simulator are described. The simulator provides a multitasking environment for the development of algorithms for parallel processors using either shared or local memories. The simulator may be used from C or FORTRAN and provides a library of subroutines for task control and message passing. The simulator produces a trace file that can be used for debugging, performance analysis, or graphical display. 9 refs., 7 figs.

Authors:
Publication Date:
Research Org.:
Oak Ridge National Lab., TN (USA)
OSTI Identifier:
5760616
Report Number(s):
ORNL/TM-9966
ON: DE86010076
DOE Contract Number:
AC05-84OR21400
Resource Type:
Technical Report
Resource Relation:
Other Information: Portions of this document are illegible in microfiche products. Original copy available until stock is exhausted
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ARRAY PROCESSORS; COMPUTERIZED SIMULATION; DEC COMPUTERS; EXECUTIVE CODES; FORTRAN; COMPUTER CODES; COMPUTERS; PROGRAMMING LANGUAGES; SIMULATION; 990200* - Mathematics & Computers

Citation Formats

Dunigan, T.H. Message-passing multiprocessor simulator. United States: N. p., 1986. Web. doi:10.2172/5760616.
Dunigan, T.H. Message-passing multiprocessor simulator. United States. doi:10.2172/5760616.
Dunigan, T.H. Thu . "Message-passing multiprocessor simulator". United States. doi:10.2172/5760616. https://www.osti.gov/servlets/purl/5760616.
@article{osti_5760616,
title = {Message-passing multiprocessor simulator},
author = {Dunigan, T.H.},
abstractNote = {The structure and use of a message-passing multiprocessor simulator are described. The simulator provides a multitasking environment for the development of algorithms for parallel processors using either shared or local memories. The simulator may be used from C or FORTRAN and provides a library of subroutines for task control and message passing. The simulator produces a trace file that can be used for debugging, performance analysis, or graphical display. 9 refs., 7 figs.},
doi = {10.2172/5760616},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu May 01 00:00:00 EDT 1986},
month = {Thu May 01 00:00:00 EDT 1986}
}

Technical Report:

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  • Parallel algorithms are presented for computing the Cholesky factorization on multiprocessors having only private local memory. Synchronization of multiple processes is based on message passing. Several possible processor interconnection networks are considered.
  • The report discusses an analytical model for analyzing the performance of a message passing multiprocessor achieving concurrency by domain decomposition, i.e., by partitioning the data domain into sub-domains, and carrying out computation on each sub-domain in a different processor. Studies on different numerical algorithms reveal that execution of an algorithm can be modelled as repetitive cycles where a cycle consists of computation followed by communication or computation with overlapped communication. The paper gives expressions for the execution times, speed-ups and efficiencies for different models of parallel algorithm execution. These expressions have been used to study how the efficiency varies withmore » different parameters such as computation-communication ratio and processor load balancing.« less
  • The report discusses an analytical model for evaluating the performance of any message passing multiprocessor achieving concurrency by domain decomposition i.e., by partitioning the data domain into sub-domains, computation on each of which is carried out in a different processor. Studies on different numerical algorithms reveal that execution of an algorithm can be modeled as repetitive cycles where a cycle consists of computation followed by communication or it may consist of computation with overlapped communication. The expression for parallel execution times and speed-ups are given for different models of algorithm execution when the data domain is partitioned into sub-domains ofmore » equal size and all the processors execute the same program. The model has been validated by measurements on a four Transputer based parallel processing system and the results reveal that the model proposed here can predict the performance to within 99% accuracy.« less
  • Two important parallel architecture types are the shared-memory architectures and the message-passing architectures. In the past, researchers working on the parallel implementations of production systems have focused either on shared-memory multiprocessors or on special-purpose architectures. Message-passing computers have not been studied. The main reasons have been the large message-passing latency (as large as a few milliseconds) and high message reception overheads (several hundred microseconds) exhibited by the first-generation message-passing computers. These overheads are too large for the parallel implementation of production systems, where it is necessary to exploit parallelism at a very fine granularity to obtain significant speed-up (subtasks executemore » about 100 machine instructions).« less
  • The design, implementation, and performance evaluation of a message passing facility (MPF) for shared memory multiprocessors are presented. The MPF is based on a message passing model conceptually similar to conversations. Participants (parallel processors) can enter or leave a conversation at any time. The message passing primitives for this model are implemented as a portable library of C function calls. The MPF is currently operational on a Sequent Balance 21000, and several parallel applications were developed and tested. Several simple benchmark programs are presented to establish interprocess communication performance for common patterns of interprocess communication. Finally, performance figures are presentedmore » for two parallel applications, linear systems solution, and iterative solution of partial differential equations.« less