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Title: The performance of software-managed multiprocessor caches on parallel numerical programs

Abstract

In recent years interest has grown in multiprocessor architectures that can have several hundred processors sharing memory and all working on solving a single problem. Such multiprocessors are characterized by a long memory access time, which makes use of cache memories very important. However, the cache coherence problem makes the use of private caches difficult. The proposed solutions to the cache coherence problem are not suitable for a large-scale multiprocessor. We proposed a different solution that relies on a compiler to manage the caches during the execution of a parallel program. In this paper we discuss the performance evaluation of private cache memories for multiprocessors in general and present the results of performance improvement for parallel numerical programs using the caches managed with compiler assistance. The effect of cache organization and other system parameters such as cache block size, cache size, and the number of processors in the system performance is shown. 18 refs., 2 figs., 7 tabs.

Authors:
;
Publication Date:
Research Org.:
Illinois Univ., Urbana (USA). Center for Supercomputing Research and Development
OSTI Identifier:
5735099
Report Number(s):
DOE/ER/25001-36; CONF-8706183-3
ON: DE88003590
DOE Contract Number:  
FG02-85ER25001
Resource Type:
Conference
Resource Relation:
Conference: ICS '87: international conference on supercomputing, Athens, Greece, 8 Jun 1987; Other Information: Paper copy only, copy does not permit microfiche production
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ARRAY PROCESSORS; MEMORY MANAGEMENT; PERFORMANCE TESTING; ALGORITHMS; BENCHMARKS; COMPUTER ARCHITECTURE; MATRICES; OPTIMIZATION; PARALLEL PROCESSING; TRANSLATORS; COMPUTER CODES; MATHEMATICAL LOGIC; PROGRAMMING; TESTING; 990210* - Supercomputers- (1987-1989)

Citation Formats

Cheong, Hoichi, and Veidenbaum, A V. The performance of software-managed multiprocessor caches on parallel numerical programs. United States: N. p., 1987. Web.
Cheong, Hoichi, & Veidenbaum, A V. The performance of software-managed multiprocessor caches on parallel numerical programs. United States.
Cheong, Hoichi, and Veidenbaum, A V. 1987. "The performance of software-managed multiprocessor caches on parallel numerical programs". United States.
@article{osti_5735099,
title = {The performance of software-managed multiprocessor caches on parallel numerical programs},
author = {Cheong, Hoichi and Veidenbaum, A V},
abstractNote = {In recent years interest has grown in multiprocessor architectures that can have several hundred processors sharing memory and all working on solving a single problem. Such multiprocessors are characterized by a long memory access time, which makes use of cache memories very important. However, the cache coherence problem makes the use of private caches difficult. The proposed solutions to the cache coherence problem are not suitable for a large-scale multiprocessor. We proposed a different solution that relies on a compiler to manage the caches during the execution of a parallel program. In this paper we discuss the performance evaluation of private cache memories for multiprocessors in general and present the results of performance improvement for parallel numerical programs using the caches managed with compiler assistance. The effect of cache organization and other system parameters such as cache block size, cache size, and the number of processors in the system performance is shown. 18 refs., 2 figs., 7 tabs.},
doi = {},
url = {https://www.osti.gov/biblio/5735099}, journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Jan 01 00:00:00 EST 1987},
month = {Thu Jan 01 00:00:00 EST 1987}
}

Conference:
Other availability
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