Cellular array processors with variable nesting depth vector control by selective enabling of left and right neighboring processor cells
This patent describes a cellular array employing processor cells arranged in an array of rows, each of the plurality of processor cells being capable of communicating with neighboring cells horizontally located in left and right directions, wherein the improvement includes: the cellular array having control means for operating the processor cells of the array to process data in variable global words of selected longer bit lengths; each of the processor cells having: a multiport RAM having a plurality of input terminals for receiving data and first and second output terminals; an arithmetic logic unit (ALU) having first and second inputs and at least one output, the first and second inputs being coupled to the first and second output terminals of the multiport RAM; pathologic means coupled to at least one output of the arithmetic logic unit, and to corresponding path logic means in neighboring cells horizontally located in left and right directions for processing local word slices.
- Assignee:
- ITT Corp., New York, NY
- Patent Number(s):
- US 4831519
- OSTI ID:
- 5688178
- Resource Relation:
- Patent File Date: Filed date 9 May 1988
- Country of Publication:
- United States
- Language:
- English
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