Multiprocessor cache design considerations
In this paper, cache design is explored for large high-performance multiprocessors with hundreds or thousands of processors and memory modules interconnected by a pipelined multi-stage network. The majority of the multiprocessor cache studies in the literature exclusively focus on the issue of cache coherence enforcement. However, there are other characteristics unique to such multiprocessors which create an environment for cache performance that is very different from that of many uniprocessors. Multiprocessor conditions are identified and modeled, including: the cost of a cache coherence enforcement scheme, the effect of a high degree of overlap between cache miss services, the cost of a pin limited data path between shared memory and caches, the effect of a high degree of data prefetching, the program behavior of a scientific workload as represented by 23 numerical subroutines, and the parallel execution of programs. This model is used to show that the cache miss ratio is not a suitable performance measure in the multiprocessors of interest and to show that the optimal cache block size in such multiprocessors is much smaller than in many uniprocessors. 31 refs., 10 figs., 1 tab.
- Research Organization:
- Illinois Univ., Urbana (USA). Center for Supercomputing Research and Development
- DOE Contract Number:
- FG02-85ER25001
- OSTI ID:
- 5546150
- Report Number(s):
- DOE/ER/25001-42; CONF-8706138-1; ON: TI88003587
- Resource Relation:
- Conference: 14. annual international symposium on computer architecture, Pittsburgh, PA, USA, 2 Jun 1987
- Country of Publication:
- United States
- Language:
- English
Similar Records
Effectiveness of caches and data prefetch buffers in large-scale shared-memory multiprocessors
Data prefetching in shared memory multiprocessors