Virtual memory cache for use in multi-processing systems
This patent describes a parallel data processor system for maintaining the consistency of data blocks, each block containing bits of data and a master flag bit. The means for maintaining consists of: a main memory for storing blocks of data, caches, each storing addressable data blocks, each cache comprising a first and second data port and each data block comprising data and a master flag bit, one data bus connecting the main memory and the first port of all caches, a processor associated with each cache and connected to the second port of its associated cache, means in each cache for allowing the processor to write into an addressed data block comprising, if the block is contained in the associated cache, means for setting the master flag in that cache, means for writing into any other cache that is sharing the block, means for resetting the master flag in all other caches, and means for allowing the processor to write into the block of the associated cache, or if the block is not contained in the associated cache, means for reading the block from another cache if any other cache has the block with the master flag set for that block, or from main memory otherwise.
- Assignee:
- Xerox Corp., Stamford, CT
- Patent Number(s):
- US 4843542
- OSTI ID:
- 5536829
- Resource Relation:
- Patent File Date: 12 Nov 1986
- Country of Publication:
- United States
- Language:
- English
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