Vector access performance in parallel memories using a skewed storage scheme
The degree to which high-speed vector processors approach their peak performance levels is closely tied to the amount of interference they encounter while accessing vectors in memory. In this paper the authors present an evaluation of a storage scheme that reduces the average memory access time in a vector-oriented architecture. A skewing scheme is used to map vector components into parallel memory modules such that, for most vector access patterns, the number of memory conflicts is reduced over that observed in interleaved parallel memory systems. Address and data buffers are used locally in ech module so that transient nonuniformities which occur in some access patterns do not degrade performance. The skewing scheme evaluated here does not eliminate all memory conflicts but it does improve the average performance of vector access over interleaved systems for a wide range of strides. It is shown that little extra hardware is required to implement the skewing scheme. Also, far fewer restrictions are placed on the number of memory modules in the system than are present in other proposed schemes.
- Research Organization:
- School of Engineering and Computer Sciences, Univ. of Texas at Dallas, Richardson, TX 75083
- OSTI ID:
- 5507904
- Journal Information:
- IEEE Trans. Comput.; (United States), Vol. C-36:12
- Country of Publication:
- United States
- Language:
- English
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