skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Design of fault tolerant programmable logic arrays for yield enhancement

Abstract

The yield (expected percentage of good chips out of a wafer) of integrated circuits (ICs) has always been crucial to the commercial success of their manufacture. One solution to the low yield problem is to improve manufacturing and testing processes, but it is very costly and quite difficult to implement within a short time. Another practical way is the use of fault-tolerant structures, which has been demonstrated in practice for high density memory chips. Programmable Logic Arrays (PLAs) have the advantages of regular structure, design simplicity, and fast turnaround time. The use of PLAs becomes increasingly popular for implementing Boolean logic functions and control blocks in the design of integrated circuit. Due to the fact that complex chips (and in particular microprocessors) can be efficiently implemented using PLAs, a trend towards manufacturing larger programmable chips is expected. In this dissertation, a fault-tolerant design for large PLAs is proposed. The fault-tolerant design achieves a full diagnosability of single and multiple stuck-at faults, bridging faults, and crosspoint faults. During the manufacturing process, faults in the PLA can be detected, located, and repaired with the spare lines. When the PLA is used in field, the structure still possesses the easily testable capability. Anmore » automatic layout generator, MRPLA, has also been developed and implemented in Sun 3/160 for generating the physical layout of the proposed fault-tolerant PLA. In addition, some important issues such as die size, speed, and yield enhancement are also addressed in this study. The results of this study show that the yield can be enhanced significantly.« less

Authors:
Publication Date:
Research Org.:
Michigan State Univ., East Lansing, MI (United States)
OSTI Identifier:
5458396
Resource Type:
Miscellaneous
Resource Relation:
Other Information: Thesis (Ph. D.)
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; INTEGRATED CIRCUITS; DESIGN; DEFECTS; DETECTION; ELECTRICAL FAULTS; FAULT TOLERANT COMPUTERS; MANUFACTURING; MEMORY DEVICES; OPTIMIZATION; PROGRAMMING; USES; COMPUTERS; DIGITAL COMPUTERS; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS; 990200* - Mathematics & Computers

Citation Formats

Chang, T Y. Design of fault tolerant programmable logic arrays for yield enhancement. United States: N. p., 1989. Web.
Chang, T Y. Design of fault tolerant programmable logic arrays for yield enhancement. United States.
Chang, T Y. Sun . "Design of fault tolerant programmable logic arrays for yield enhancement". United States.
@article{osti_5458396,
title = {Design of fault tolerant programmable logic arrays for yield enhancement},
author = {Chang, T Y},
abstractNote = {The yield (expected percentage of good chips out of a wafer) of integrated circuits (ICs) has always been crucial to the commercial success of their manufacture. One solution to the low yield problem is to improve manufacturing and testing processes, but it is very costly and quite difficult to implement within a short time. Another practical way is the use of fault-tolerant structures, which has been demonstrated in practice for high density memory chips. Programmable Logic Arrays (PLAs) have the advantages of regular structure, design simplicity, and fast turnaround time. The use of PLAs becomes increasingly popular for implementing Boolean logic functions and control blocks in the design of integrated circuit. Due to the fact that complex chips (and in particular microprocessors) can be efficiently implemented using PLAs, a trend towards manufacturing larger programmable chips is expected. In this dissertation, a fault-tolerant design for large PLAs is proposed. The fault-tolerant design achieves a full diagnosability of single and multiple stuck-at faults, bridging faults, and crosspoint faults. During the manufacturing process, faults in the PLA can be detected, located, and repaired with the spare lines. When the PLA is used in field, the structure still possesses the easily testable capability. An automatic layout generator, MRPLA, has also been developed and implemented in Sun 3/160 for generating the physical layout of the proposed fault-tolerant PLA. In addition, some important issues such as die size, speed, and yield enhancement are also addressed in this study. The results of this study show that the yield can be enhanced significantly.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1989},
month = {1}
}

Miscellaneous:
Other availability
Please see Document Availability for additional information on obtaining the full-text document. Library patrons may search WorldCat to identify libraries that may hold this item.

Save / Share: