Throughput analysis of cache-based multiprocessors with multiple buses

Journal Article · Fri Jan 01 00:00:00 EST 1988 · IEEE Trans. Comput.; (United States)

DOI:https://doi.org/10.1109/12.75139· OSTI ID:5410790

Dubois, M

In this paper, the performance of cache-based multiprocessors for general-purpose computing and for multi-tasking is analyzed with simple throughput models. A private cache is associated with each processor, and multiple buses connect the processors to the shared, interleaved memory. Simple models based on dynamic instruction mix statistics are introduced to evaluate upper bounds on the throughput when independent tasks are run on each processor. With these models, one can obtain a first estimate of the MIPS rate of a multiprocessor. The authors then present analytical models to evaluate the throughput and efficiency of different cache-based systems for a particular multitasked algorithm, namely the Successive Over-Relaxation algorithm (SOR). The SOR algorithm is efficient for solving partial differential equations (PDE's) numerically in a multiprocessor. Parallelism is obtained naturally by partitioning the data and applying the same operator to each data partition. They identify locality levels and read/write sharing sets in the kernel of the SOR algorithm with red/black ordering of the iterates and evaluate the critical cache sizes capturing each locality level. Critical cache sizes define ranges of cache sizes within which different models apply. Besides showing performance of SOR in multiprocessors, this paper illustrates techniques that can be used to predict the suitability of cache-based multiprocessors for specific algorithms.

• Research Organization: Dept. of Electrical Engineering-Systems, Univ. of Southern California, Los Angeles, CA 90089-0781 (USA)
• OSTI ID: 5410790
• Journal Information: IEEE Trans. Comput.; (United States), Vol. 37:1
• Country of Publication: United States
• Language: English

Related Subjects

99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
ARRAY PROCESSORS
PARTIAL DIFFERENTIAL EQUATIONS
ALGORITHMS
SUPERCOMPUTERS
COMPUTERIZED SIMULATION
PARALLEL PROCESSING
EFFICIENCY
MEMORY DEVICES
PERFORMANCE
STATISTICS
COMPUTERS
DIFFERENTIAL EQUATIONS
DIGITAL COMPUTERS
EQUATIONS
MATHEMATICAL LOGIC
MATHEMATICS
PROGRAMMING
SIMULATION
990210* - Supercomputers- (1987-1989)