Vector processing
An apparatus is described for adapting a scalar data processor having a cache memory connected between main memory and a central processing unit, for efficient vector processing including: means for defining separate scalar and vector data areas in the cache memory, vector mode selection means for selectively enabling access to either the vector or scalar data areas of the cache memory, cache memory addressing means including separate vector and scalar addressing means responsive to the vector mode selection means and the central processing unit for accessing either the vector or scalar data areas of the cache memory, wherein the central processing unit includes: a pair of operand registers, and a result register, coupling means for providing a data path from the operand registers to an ALU and a further data path from an ALU to the result register, second coupling means for providing a data path from the cache memory to one of the operand registers and to the result register; an output buffer; third coupling means providing a data path from either of the operand registers to the second coupling means and to the output buffer; fourth coupling means providing a data path from the second coupling means or the output buffer to the cache memory; and fifth coupling means providing a data path from the result register to either of the operand registers.
- Assignee:
- IBM Corp., Armonk, NY
- Patent Number(s):
- US 4594682
- OSTI ID:
- 5404730
- Resource Relation:
- Patent File Date: Filed date 22 Dec 1982
- Country of Publication:
- United States
- Language:
- English
Similar Records
Data Locality Enhancement of Dynamic Simulations for Exascale Computing (Final Report)
Multiprocessor memory contention