High resolution digital delay timer
A high resolution delay timer for generating an output pulse following a trigger pulse at a time delay interval preset with a resolution which is high relative to a low resolution available from supplied clock pulses is described comprising: first lumped constant delay means for inputting the trigger pulse and generating a first output signal at predetermined interpolation intervals corresponding to the high resolution; first latch means in series connection with the first lumped constant delay means for detecting edges of the supplied clock pulse and latching the first output signal in response to a first one of the edges after the trigger pulse to form first high resolution synchronizing delay data; input means for presetting a selected time delay interval with a first timing portion having a relatively low resolution and with a second timing portion having the high resolution; timer means in series with the input means and including counter means responsive to the first timing portion for relatively low resolution timing and second lumped constant delay means responsive to the second timing portion for timing at the high resolution wherein an internal pulse is generated at a delay temporally related to the preset time interval; circuit means in series with the timer means and receiving the internal pulse for initiating generation of second high resolution synchronizing delay data; and logic circuit means connected to receive the first and second synchronizing delay data in parallel for logically combining the first and second delay data and generating the output pulse synchronized with the trigger pulse and delayed by the preset high resolution time delay interval.
- Assignee:
- Dept. of Energy, Washington, DC
- Patent Number(s):
- US 4719375
- OSTI ID:
- 5385573
- Resource Relation:
- Patent File Date: Filed date 9 May 1986
- Country of Publication:
- United States
- Language:
- English
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