Hardware multiplier processor
A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.
- DOE Contract Number:
- AC04-76DP00789
- Assignee:
- SNL; EDB-84-039551
- Application Number:
- ON: DE84006174
- OSTI ID:
- 5372623
- Country of Publication:
- United States
- Language:
- English
Similar Records
Hardware multiplier processor
MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY
Related Subjects
42 ENGINEERING
MICROPROCESSORS
SEMICONDUCTOR STORAGE DEVICES
DATA PROCESSING
DATA TRANSMISSION
DESIGN
PARALLEL PROCESSING
PERFORMANCE
COMMUNICATIONS
COMPUTERS
ELECTRONIC CIRCUITS
MEMORY DEVICES
MICROELECTRONIC CIRCUITS
PROCESSING
PROGRAMMING
SEMICONDUCTOR DEVICES
990200* - Mathematics & Computers
420800 - Engineering- Electronic Circuits & Devices- (-1989)