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Title: Fault-tolerant corrector/detector chip for high-speed data processing

Abstract

An internally fault-tolerant data error detection and correction integrated circuit device and a method of operating same is described. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the devicemore » to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented. 8 figures.« less

Inventors:
; ; ;
Publication Date:
OSTI Identifier:
5211657
Patent Number(s):
US 5291496; A
Application Number:
PPN: US 7-599606
Assignee:
Dept. of Energy, Washington, DC () SNL; EDB-94-066244
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent
Resource Relation:
Patent File Date: 18 Oct 1990
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; MICROPROCESSORS; DESIGN; DATA TRANSMISSION; FAULT TOLERANT COMPUTERS; INTEGRATED CIRCUITS; COMMUNICATIONS; COMPUTERS; DIGITAL COMPUTERS; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS; 990200* - Mathematics & Computers

Citation Formats

Andaleon, D.D., Napolitano, L.M. Jr., Redinbo, G.R., and Shreeve, W.O.. Fault-tolerant corrector/detector chip for high-speed data processing. United States: N. p., 1994. Web.
Andaleon, D.D., Napolitano, L.M. Jr., Redinbo, G.R., & Shreeve, W.O.. Fault-tolerant corrector/detector chip for high-speed data processing. United States.
Andaleon, D.D., Napolitano, L.M. Jr., Redinbo, G.R., and Shreeve, W.O.. Tue . "Fault-tolerant corrector/detector chip for high-speed data processing". United States.
@article{osti_5211657,
title = {Fault-tolerant corrector/detector chip for high-speed data processing},
author = {Andaleon, D.D. and Napolitano, L.M. Jr. and Redinbo, G.R. and Shreeve, W.O.},
abstractNote = {An internally fault-tolerant data error detection and correction integrated circuit device and a method of operating same is described. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented. 8 figures.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1994},
month = {3}
}