skip to main content
OSTI.GOV title logo U.S. Department of Energy
Office of Scientific and Technical Information

Title: Multiprocessor memory contention

Abstract

Caches are frequently incorporated in processor architectures to increase the effective memory speed and to reduce memory contention. However, task switches and the coherency problems of large n-way, mainframe-class multiprocessors lessen the effectiveness of cache architectures for general-purpose applications. A proposed alternative approach is to increase the effective memory bandwidth and decrease memory-access delays through instruction prefetch, operand buffering, highly interleave memory, and multiple-word width processor-memory data paths. This approach was evaluated by comparing cache and noncache system performance, using discrete-event simulation. Since the performance of a multiprocessor architecture is a function of its operating environment was well as its design, the system workload was defined. General-purpose applications, running under multitasking operating systems, were characterized with respect to addressing patterns, paging rates, and frequency of input/output operations. The proposed noncache architecture was found to have performance comparable to that of the cache architectures and obviated then need to solve the cache coherency problem.

Authors:
Publication Date:
Research Org.:
George Washington Univ., Washington, DC (USA)
OSTI Identifier:
5173132
Resource Type:
Thesis/Dissertation
Resource Relation:
Other Information: Thesis (Ph. D.)
Country of Publication:
United States
Language:
English
Subject:
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE; ARRAY PROCESSORS; MEMORY MANAGEMENT; COMPUTER ARCHITECTURE; SIMULATION; PERFORMANCE; TASK SCHEDULING; DATA PROCESSING; PROCESSING; 990200* - Mathematics & Computers

Citation Formats

Knadler, Jr, C E. Multiprocessor memory contention. United States: N. p., 1989. Web.
Knadler, Jr, C E. Multiprocessor memory contention. United States.
Knadler, Jr, C E. Sun . "Multiprocessor memory contention". United States.
@article{osti_5173132,
title = {Multiprocessor memory contention},
author = {Knadler, Jr, C E},
abstractNote = {Caches are frequently incorporated in processor architectures to increase the effective memory speed and to reduce memory contention. However, task switches and the coherency problems of large n-way, mainframe-class multiprocessors lessen the effectiveness of cache architectures for general-purpose applications. A proposed alternative approach is to increase the effective memory bandwidth and decrease memory-access delays through instruction prefetch, operand buffering, highly interleave memory, and multiple-word width processor-memory data paths. This approach was evaluated by comparing cache and noncache system performance, using discrete-event simulation. Since the performance of a multiprocessor architecture is a function of its operating environment was well as its design, the system workload was defined. General-purpose applications, running under multitasking operating systems, were characterized with respect to addressing patterns, paging rates, and frequency of input/output operations. The proposed noncache architecture was found to have performance comparable to that of the cache architectures and obviated then need to solve the cache coherency problem.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {1989},
month = {1}
}

Thesis/Dissertation:
Other availability
Please see Document Availability for additional information on obtaining the full-text document. Library patrons may search WorldCat to identify libraries that hold this thesis or dissertation.

Save / Share: