Timing and area optimization of CMOS combinational-logic circuits accounting for total-dose radiation effects

Conference · Tue Dec 01 00:00:00 EST 1987 · IEEE Trans. Nucl. Sci.; (United States)

OSTI ID:5131214

Gyuresik, R S; Thomas, D W; Gallimore, R H; Bhuva, B L; Kerns, S E

An algorithm for optimizing CMOS VLSI combinational logic circuits for operation in total-dose environments is presented. The width-to-length ratios of the MOS transistors are determined which allow the circuit to meet specified timing requirements while minimizing circuit area. The logic circuit is modeled by an equivalent resistor-capacitor (RC) network, where the resistors and capacitors are functions of transistor width-to-length ratios. The total-dose radiation dependence is modeled as a variation in the resistors. The algorithm has been implemented and tested on example circuits, and the results have been verified using SPICE.

• Research Organization: Dept. of Electrical and Computer Engineering, Box 7911, North Carolina State Univ., Raleigh, NC 27695-7911 (US)
• OSTI ID: 5131214
• Report Number(s): CONF-8707112-; TRN: 88-019182
• Journal Information: IEEE Trans. Nucl. Sci.; (United States), Vol. NS-34:6; Conference: Annual conference on nuclear and space radiation effects, Snowmass Village, CO, USA, 28 Jul 1987
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
99 GENERAL AND MISCELLANEOUS//MATHEMATICS, COMPUTING, AND INFORMATION SCIENCE
42 ENGINEERING
MOS TRANSISTORS
PERFORMANCE TESTING
PHYSICAL RADIATION EFFECTS
SEMICONDUCTOR RESISTORS
ALGORITHMS
CAPACITORS
LOGIC CIRCUITS
OPTIMIZATION
RADIATION DOSES
S CODES
TIMING CIRCUITS
VERIFICATION
COMPUTER CODES
DOSES
ELECTRICAL EQUIPMENT
ELECTRONIC CIRCUITS
EQUIPMENT
MATHEMATICAL LOGIC
RADIATION EFFECTS
RESISTORS
SEMICONDUCTOR DEVICES
TESTING
TRANSISTORS
360605* - Materials- Radiation Effects
990230 - Mathematics & Mathematical Models- (1987-1989)
420800 - Engineering- Electronic Circuits & Devices- (-1989)