High performance static latches with complete single event upset immunity

Patent · Tue Apr 26 00:00:00 EDT 1994

OSTI ID:5037725

Corbett, W T; Weaver, H T

An asymmetric response latch providing immunity to single event upset without loss of speed is described. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states. 5 figures.

• DOE Contract Number: AC04-76DP00789
• Assignee: Dept. of Energy, Washington, DC (United States)
• Patent Number(s): US 5307142; A
• Application Number: PPN: US 7-793084
• OSTI ID: 5037725
• Resource Relation: Patent File Date: 15 Nov 1991
• Country of Publication: United States
• Language: English

Related Subjects

42 ENGINEERING
ELECTRONIC EQUIPMENT
EQUIPMENT PROTECTION DEVICES
DESIGN
FAILURES
PERFORMANCE
EQUIPMENT
426000* - Engineering- Components
Electron Devices & Circuits- (1990-)