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Title: A fault-tolerant corrector/detector chip for high-speed data processing

Abstract

An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of themore » device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented.« less

Inventors:
; ; ;
Publication Date:
Research Org.:
Sandia National Labs., Albuquerque, NM (United States)
Sponsoring Org.:
USDOE; USDOE, Washington, DC (United States)
OSTI Identifier:
5021813
Patent Number(s):
PATENTS-US-A7599606
Application Number:
ON: DE92016378; PPN: US 7-599606
Assignee:
Dept. of Energy SNL; EDB-92-118762
DOE Contract Number:  
AC04-76DP00789
Resource Type:
Patent Application
Country of Publication:
United States
Language:
English
Subject:
42 ENGINEERING; INTEGRATED CIRCUITS; DESIGN; CORRECTIONS; DATA PROCESSING; INVENTIONS; MICROPROCESSORS; COMPUTERS; ELECTRONIC CIRCUITS; MICROELECTRONIC CIRCUITS; PROCESSING; 426000* - Engineering- Components, Electron Devices & Circuits- (1990-)

Citation Formats

Andaleon, D.D., Napolitano, L.M. Jr., Redinbo, G.R., and Shreeve, W.O. A fault-tolerant corrector/detector chip for high-speed data processing. United States: N. p., 1990. Web.
Andaleon, D.D., Napolitano, L.M. Jr., Redinbo, G.R., & Shreeve, W.O. A fault-tolerant corrector/detector chip for high-speed data processing. United States.
Andaleon, D.D., Napolitano, L.M. Jr., Redinbo, G.R., and Shreeve, W.O. Thu . "A fault-tolerant corrector/detector chip for high-speed data processing". United States.
@article{osti_5021813,
title = {A fault-tolerant corrector/detector chip for high-speed data processing},
author = {Andaleon, D.D. and Napolitano, L.M. Jr. and Redinbo, G.R. and Shreeve, W.O.},
abstractNote = {An internally fault-tolerant data error detection and correction integrated circuit device (10) and a method of operating same. The device functions as a bidirectional data buffer between a 32-bit data processor and the remainder of a data processing system and provides a 32-bit datum is provided with a relatively short eight bits of data-protecting parity. The 32-bits of data by eight bits of parity is partitioned into eight 4-bit nibbles and two 4-bit nibbles, respectively. For data flowing towards the processor the data and parity nibbles are checked in parallel and in a single operation employing a dual orthogonal basis technique. The dual orthogonal basis increase the efficiency of the implementation. Any one of ten (eight data, two parity) nibbles are correctable if erroneous, or two different erroneous nibbles are detectable. For data flowing away from the processor the appropriate parity nibble values are calculated and transmitted to the system along with the data. The device regenerates parity values for data flowing in either direction and compares regenerated to generated parity with a totally self-checking equality checker. As such, the device is self-validating and enabled to both detect and indicate an occurrence of an internal failure. A generalization of the device to protect 64-bit data with 16-bit parity to protect against byte-wide errors is also presented.},
doi = {},
journal = {},
number = ,
volume = ,
place = {United States},
year = {Thu Oct 18 00:00:00 EDT 1990},
month = {Thu Oct 18 00:00:00 EDT 1990}
}