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Title: Constant fan-in digital neural networks are VLSI-optimal

Abstract

The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.

Authors:
Publication Date:
Research Org.:
Los Alamos National Lab. (LANL), Los Alamos, NM (United States)
Sponsoring Org.:
USDOE Assistant Secretary for Human Resources and Administration, Washington, DC (United States)
OSTI Identifier:
486012
Report Number(s):
LA-UR-97-61; CONF-9507268-1
ON: DE97003400; TRN: 97:003923
DOE Contract Number:  
W-7405-ENG-36
Resource Type:
Conference
Resource Relation:
Conference: Mathematics of neural networks and applications, Oxford (United Kingdom), 3-7 Jul 1995; Other Information: PBD: 1995
Country of Publication:
United States
Language:
English
Subject:
99 MATHEMATICS, COMPUTERS, INFORMATION SCIENCE, MANAGEMENT, LAW, MISCELLANEOUS; 42 ENGINEERING NOT INCLUDED IN OTHER CATEGORIES; MICROELECTRONIC CIRCUITS; LIMITING VALUES; NEURAL NETWORKS; OPTIMIZATION

Citation Formats

Beiu, V. Constant fan-in digital neural networks are VLSI-optimal. United States: N. p., 1995. Web.
Beiu, V. Constant fan-in digital neural networks are VLSI-optimal. United States.
Beiu, V. 1995. "Constant fan-in digital neural networks are VLSI-optimal". United States. https://www.osti.gov/servlets/purl/486012.
@article{osti_486012,
title = {Constant fan-in digital neural networks are VLSI-optimal},
author = {Beiu, V},
abstractNote = {The paper presents a theoretical proof revealing an intrinsic limitation of digital VLSI technology: its inability to cope with highly connected structures (e.g. neural networks). We are in fact able to prove that efficient digital VLSI implementations (known as VLSI-optimal when minimizing the AT{sup 2} complexity measure - A being the area of the chip, and T the delay for propagating the inputs to the outputs) of neural networks are achieved for small-constant fan-in gates. This result builds on quite recent ones dealing with a very close estimate of the area of neural networks when implemented by threshold gates, but it is also valid for classical Boolean gates. Limitations and open questions are presented in the conclusions.},
doi = {},
url = {https://www.osti.gov/biblio/486012}, journal = {},
number = ,
volume = ,
place = {United States},
year = {1995},
month = {12}
}

Conference:
Other availability
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