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Title: Design optimization of radiation-hardened CMOS integrated circuits

Abstract

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented. (auth)

Publication Date:
Research Org.:
Sandia Labs., Albuquerque, NM
OSTI Identifier:
4094839
NSA Number:
NSA-33-020336
Resource Type:
Conference
Journal Name:
IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2208-2213
Additional Journal Information:
Conference: Annual conference on nuclear and space radiation effects, Arcata, CA, 14 Jul 1975; Other Information: Orig. Receipt Date: 30-JUN-76
Country of Publication:
United States
Language:
English
Subject:
N46300* -Instrumentation-Radiation Effects on Instrument Components, Instruments, or Electronic Systems; 440200* -Instrumentation-Radiation Effects on Instrument Components, Instruments, or Electronic Systems; *INTEGRATED CIRCUITS- RADIATION HARDENING; *MOS TRANSISTORS- RADIATION HARDENING; DESIGN; OPTIMIZATION

Citation Formats

. Design optimization of radiation-hardened CMOS integrated circuits. United States: N. p., 1975. Web.
. Design optimization of radiation-hardened CMOS integrated circuits. United States.
. Mon . "Design optimization of radiation-hardened CMOS integrated circuits". United States.
@article{osti_4094839,
title = {Design optimization of radiation-hardened CMOS integrated circuits},
author = {},
abstractNote = {Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented. (auth)},
doi = {},
journal = {IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2208-2213},
number = ,
volume = ,
place = {United States},
year = {1975},
month = {12}
}

Conference:
Other availability
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