Design optimization of radiation-hardened CMOS integrated circuits
Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented. (auth)
- Research Organization:
- Sandia Labs., Albuquerque, NM
- NSA Number:
- NSA-33-020336
- OSTI ID:
- 4094839
- Journal Information:
- IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2208-2213, Conference: Annual conference on nuclear and space radiation effects, Arcata, CA, 14 Jul 1975; Other Information: Orig. Receipt Date: 30-JUN-76
- Country of Publication:
- United States
- Language:
- English
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*INTEGRATED CIRCUITS- RADIATION HARDENING
*MOS TRANSISTORS- RADIATION HARDENING
DESIGN
OPTIMIZATION