Process optimization of radiation-hardened CMOS integrated circuits

Conference · Mon Dec 01 00:00:00 EST 1975 · IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2151-2156

OSTI ID:4090108

Derbenwick, G F; Gregory, B L

The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 10$sup 8$ rads (Si) have been fabricated. Restrictions that the observed physical dependences place upon possible models for the traps responsible for radiation-induced charging in SiO$sub 2$ are discussed. (auth)

• Research Organization: Sandia Labs., Albuquerque, NM
• NSA Number: NSA-33-020331
• OSTI ID: 4090108
• Journal Information: IEEE Trans. Nucl. Sci., v. NS-22, no. 6, pp. 2151-2156, Conference: Annual conference on nuclear and space radiation effects, Arcata, CA, 14 Jul 1975; Other Information: Orig. Receipt Date: 30-JUN-76
• Country of Publication: United States
• Language: English

Related Subjects

N46300* -Instrumentation-Radiation Effects on Instrument Components
Instruments
or Electronic Systems
440200* -Instrumentation-Radiation Effects on Instrument Components
Instruments
or Electronic Systems
*INTEGRATED CIRCUITS- RADIATION HARDENING
*MOS TRANSISTORS- RADIATION HARDENING
FABRICATION
OPTIMIZATION
PHYSICAL RADIATION EFFECTS