Solutions and debugging for data consistency in multiprocessors with noncoherent caches
- IBM Israel, Haifa (Israel)
- Motorola MMTG Division, Austin, TX (United States)
- IBM Austin, TX (United States)
We analyze two important problems that arise in shared-memory multiprocessor systems. The stale data problem involves ensuring that data items in local memory of individual processors are current, independent of writes done by other processors. False sharing occurs when two processors have copies of the same shared data block but update different portions of the block. The false sharing problem involves guaranteeing that subsequent writes are properly combined. In modern architectures these problems are usually solved in hardware, by exploiting mechanisms for hardware controlled cache consistency. This leads to more expensive and nonscalable designs. Therefore, we are concentrating on software methods for ensuring cache consistency that would allow for affordable and scalable multiprocessing systems. Unfortunately, providing software control is nontrivial, both for the compiler writer and for the application programmer. For this reason we are developing a debugging environment that will facilitate the development of compiler-based techniques and will help the programmer to tune his or her application using explicit cache management mechanisms. We extend the notion of a race condition for IBM Shared Memory System POWER/4, taking into consideration its noncoherent caches, and propose techniques for detection of false sharing problems. Identification of the stale data problem is discussed as well, and solutions are suggested.
- Sponsoring Organization:
- USDOE
- OSTI ID:
- 379415
- Journal Information:
- International Journal of Parallel Programming, Vol. 23, Issue 1; Other Information: PBD: Feb 1995
- Country of Publication:
- United States
- Language:
- English
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