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Title: A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces

Abstract

The fundamental limitation in the measurement accuracy of detector/sensor low-level signals is determined by the noise of the electronic channels attached to the detector/sensor elements. In multichannel systems--such as silicon microstrip tracking detector systems for colliding particle experiments--where as many as 10 million detector/sensor elements are attached to the corresponding electronic channels, the power dissipation per channel has to be minimized. Furthermore, in a multichannel system, it is desirable to have a calibrationless system (or self-calibration system) so that the overall system performance is insensitive to the integrated circuit implementation nonidealities such as channel-to-channel offset and gain mismatches. This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A-to-D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 {mu} single-poly double-metal CMOS P-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1,800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electronsmore » while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%.« less

Authors:
; ;  [1]
  1. Univ. of Pennsylvania, Philadelphia, PA (United States)
Publication Date:
OSTI Identifier:
32066
Resource Type:
Journal Article
Journal Name:
IEEE Journal of Solid-State Circuits
Additional Journal Information:
Journal Volume: 30; Journal Issue: 2; Other Information: PBD: Feb 1995
Country of Publication:
United States
Language:
English
Subject:
44 INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS; RADIATION DETECTORS; INTEGRATED CIRCUITS; DESIGN; PERFORMANCE; EXPERIMENTAL DATA; POWER LOSSES; SAMPLING; ANALOG-TO-DIGITAL CONVERTERS

Citation Formats

Tedja, S, Van der Spiegel, J, and Williams, H H. A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces. United States: N. p., 1995. Web. doi:10.1109/4.341737.
Tedja, S, Van der Spiegel, J, & Williams, H H. A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces. United States. https://doi.org/10.1109/4.341737
Tedja, S, Van der Spiegel, J, and Williams, H H. Wed . "A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces". United States. https://doi.org/10.1109/4.341737.
@article{osti_32066,
title = {A CMOS low-noise and low-power charge sampling integrated circuit for capacitive detector/sensor interfaces},
author = {Tedja, S and Van der Spiegel, J and Williams, H H},
abstractNote = {The fundamental limitation in the measurement accuracy of detector/sensor low-level signals is determined by the noise of the electronic channels attached to the detector/sensor elements. In multichannel systems--such as silicon microstrip tracking detector systems for colliding particle experiments--where as many as 10 million detector/sensor elements are attached to the corresponding electronic channels, the power dissipation per channel has to be minimized. Furthermore, in a multichannel system, it is desirable to have a calibrationless system (or self-calibration system) so that the overall system performance is insensitive to the integrated circuit implementation nonidealities such as channel-to-channel offset and gain mismatches. This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A-to-D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 {mu} single-poly double-metal CMOS P-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1,800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%.},
doi = {10.1109/4.341737},
url = {https://www.osti.gov/biblio/32066}, journal = {IEEE Journal of Solid-State Circuits},
number = 2,
volume = 30,
place = {United States},
year = {1995},
month = {2}
}