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Title: A low noise amplifier-shaper with tail correction for the STAR detector

Abstract

A 16 channel low noise amplifier shaper has been designed for the STAR particle detector of the RHIC accelerator. The STAR Amplifier-Shaper (SAS) includes a pole/zero network which cancels the long tail of the Time Projection Chamber (TPC) signal. The tail correction can be adjusted depending on the type of gas used in the TPC. The SAS equivalent noise charge is 900e{sup {minus}}{sub RMS} with 25 pf detector capacitance (the test board having 7.7 pF of parasitic capacitance), and with 80 ns shaping time (step response). The measured noise slope is 13.7e{sup {minus}}{sub RMS}/pF. The shaper pulse FWHM is adjusted at 180 ns (detector response) with +/{minus}4% variation over the entire dynamic range. The shaping time and the tail correction are adjusted with external voltages using MOS resistors. The gain is 16 mV/fC with a linearity of 4%. The crosstalk is about 0.36% which have a negligible effect on the position resolution. The circuit also includes as on-chip calibration system in which the test input charge is controlled by a DC voltage. The output buffer drives a 2 V swing on 50 pF output load for a total power consumption of less than 750 mW (+/{minus}5 Volt supply). On-chip protectionmore » diodes have also been integrated. The full custom chip has been integrated in the CMOS ORBIT 1.2 {micro}m technology with double polysilicon capacitors.« less

Authors:
; ;  [1]
  1. Lawrence Berkeley National Lab., CA (United States); and others
Publication Date:
OSTI Identifier:
276449
Report Number(s):
CONF-951073-
Journal ID: IETNAE; ISSN 0018-9499; TRN: 96:017974
DOE Contract Number:  
AC03-76SF00098
Resource Type:
Journal Article
Journal Name:
IEEE Transactions on Nuclear Science
Additional Journal Information:
Journal Volume: 43; Journal Issue: 3Pt2; Conference: IEEE nuclear science symposium and medical imaging conference, San Francisco, CA (United States), 21-28 Oct 1995; Other Information: PBD: Jun 1996
Country of Publication:
United States
Language:
English
Subject:
44 INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS; 43 PARTICLE ACCELERATORS; BROOKHAVEN RHIC; TIME PROJECTION CHAMBERS; PULSE CIRCUITS; DESIGN; ANALOG SYSTEMS; DIGITIZERS; PULSE AMPLIFIERS; PULSE SHAPERS

Citation Formats

Beuville, E, Barale, P, and Bieser, F. A low noise amplifier-shaper with tail correction for the STAR detector. United States: N. p., 1996. Web. doi:10.1109/23.507158.
Beuville, E, Barale, P, & Bieser, F. A low noise amplifier-shaper with tail correction for the STAR detector. United States. https://doi.org/10.1109/23.507158
Beuville, E, Barale, P, and Bieser, F. Sat . "A low noise amplifier-shaper with tail correction for the STAR detector". United States. https://doi.org/10.1109/23.507158.
@article{osti_276449,
title = {A low noise amplifier-shaper with tail correction for the STAR detector},
author = {Beuville, E and Barale, P and Bieser, F},
abstractNote = {A 16 channel low noise amplifier shaper has been designed for the STAR particle detector of the RHIC accelerator. The STAR Amplifier-Shaper (SAS) includes a pole/zero network which cancels the long tail of the Time Projection Chamber (TPC) signal. The tail correction can be adjusted depending on the type of gas used in the TPC. The SAS equivalent noise charge is 900e{sup {minus}}{sub RMS} with 25 pf detector capacitance (the test board having 7.7 pF of parasitic capacitance), and with 80 ns shaping time (step response). The measured noise slope is 13.7e{sup {minus}}{sub RMS}/pF. The shaper pulse FWHM is adjusted at 180 ns (detector response) with +/{minus}4% variation over the entire dynamic range. The shaping time and the tail correction are adjusted with external voltages using MOS resistors. The gain is 16 mV/fC with a linearity of 4%. The crosstalk is about 0.36% which have a negligible effect on the position resolution. The circuit also includes as on-chip calibration system in which the test input charge is controlled by a DC voltage. The output buffer drives a 2 V swing on 50 pF output load for a total power consumption of less than 750 mW (+/{minus}5 Volt supply). On-chip protection diodes have also been integrated. The full custom chip has been integrated in the CMOS ORBIT 1.2 {micro}m technology with double polysilicon capacitors.},
doi = {10.1109/23.507158},
url = {https://www.osti.gov/biblio/276449}, journal = {IEEE Transactions on Nuclear Science},
number = 3Pt2,
volume = 43,
place = {United States},
year = {1996},
month = {6}
}