Simulated optimum gate and encapsulant properties for a refractory gate GaAs metal-semiconductor field effect transistor during annealing
Abstract
The stress distribution in a refractory gate GaAs substrate during annealing was calculated by computer simulation, using the finite element method. Simulations were used to investigate the correlation between the thermal expansion coefficient of the gate and the encapsulant internal stress. The condition in which minimum or no dislocations were induced into the GaAs substrate were studied. It was demonstrate that the best thermal expansion coefficient value of the gate was close to the value that was reported for tungsten. It was concluded that, by controlling the encapsulant thermal stress of SiO{sub 2} or SiN encapsulant, during high temperature annealing, a dislocation-free GaAs substrate could be obtained. 6 refs., 6 figs., 1 tab.
- Authors:
-
- Functional Devices Research Lab., Kanaguawa (Japan)
- NEC Corp., Shiga (Japan)
- Publication Date:
- OSTI Identifier:
- 249820
- Resource Type:
- Journal Article
- Journal Name:
- Journal of Vacuum Science and Technology. B, Microelectronics Processing and Phenomena
- Additional Journal Information:
- Journal Volume: 11; Journal Issue: 2; Other Information: PBD: Mar-Apr 1993
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 36 MATERIALS SCIENCE; 99 MATHEMATICS, COMPUTERS, INFORMATION SCIENCE, MANAGEMENT, LAW, MISCELLANEOUS; GALLIUM ARSENIDES; DISLOCATIONS; ENCAPSULATION; PHYSICAL PROPERTIES; SILICA; STRESSES; SILICON NITRIDES; ANNEALING; FINITE ELEMENT METHOD; THERMAL EXPANSION; FIELD EFFECT TRANSISTORS; TUNGSTEN ALLOYS
Citation Formats
Kitajo, S, and Kanamori, M. Simulated optimum gate and encapsulant properties for a refractory gate GaAs metal-semiconductor field effect transistor during annealing. United States: N. p., 1993.
Web. doi:10.1116/1.586697.
Kitajo, S, & Kanamori, M. Simulated optimum gate and encapsulant properties for a refractory gate GaAs metal-semiconductor field effect transistor during annealing. United States. https://doi.org/10.1116/1.586697
Kitajo, S, and Kanamori, M. 1993.
"Simulated optimum gate and encapsulant properties for a refractory gate GaAs metal-semiconductor field effect transistor during annealing". United States. https://doi.org/10.1116/1.586697.
@article{osti_249820,
title = {Simulated optimum gate and encapsulant properties for a refractory gate GaAs metal-semiconductor field effect transistor during annealing},
author = {Kitajo, S and Kanamori, M},
abstractNote = {The stress distribution in a refractory gate GaAs substrate during annealing was calculated by computer simulation, using the finite element method. Simulations were used to investigate the correlation between the thermal expansion coefficient of the gate and the encapsulant internal stress. The condition in which minimum or no dislocations were induced into the GaAs substrate were studied. It was demonstrate that the best thermal expansion coefficient value of the gate was close to the value that was reported for tungsten. It was concluded that, by controlling the encapsulant thermal stress of SiO{sub 2} or SiN encapsulant, during high temperature annealing, a dislocation-free GaAs substrate could be obtained. 6 refs., 6 figs., 1 tab.},
doi = {10.1116/1.586697},
url = {https://www.osti.gov/biblio/249820},
journal = {Journal of Vacuum Science and Technology. B, Microelectronics Processing and Phenomena},
number = 2,
volume = 11,
place = {United States},
year = {Mon Mar 01 00:00:00 EST 1993},
month = {Mon Mar 01 00:00:00 EST 1993}
}