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Efficacy of Spatial and Temporal RHBD Techniques at Advanced Bulk FinFET Technology Nodes

Journal Article · · IEEE Transactions on Nuclear Science
 [1];  [2];  [3];  [2];  [2]
  1. Electrical and Computer Engineering Department, Vanderbilt University, Nashville, TN, USA; OSTI
  2. Electrical and Computer Engineering Department, Vanderbilt University, Nashville, TN, USA
  3. Broadcom Inc., San Jose, CA, USA

Not provided.

Research Organization:
Krell Institute, Ames, IA (United States)
Sponsoring Organization:
USDOE National Nuclear Security Administration (NNSA)
DOE Contract Number:
NA0003960
OSTI ID:
2417930
Journal Information:
IEEE Transactions on Nuclear Science, Journal Name: IEEE Transactions on Nuclear Science Journal Issue: 8 Vol. 70; ISSN 0018-9499
Publisher:
IEEE
Country of Publication:
United States
Language:
English

References (30)

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SE Response of Guard-Gate FF in 16- and 7-nm Bulk FinFET Technologies journal July 2020
Charge Collection and Charge Sharing in a 130 nm CMOS Technology journal December 2006
Single-Event Upsets in a 7-nm Bulk FinFET Technology With Analysis of Threshold Voltage Dependence journal May 2021
Analysis of Bulk FinFET Structural Effects on Single-Event Cross Sections journal January 2017
Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node journal January 2019
Neutron- and Proton-Induced Single Event Upsets for D- and DICE-Flip/Flop Designs at a 40 nm Technology Node journal June 2011
High Performance and Yield for Super Steep Retrograde Wells (SSRW) by Well Implant / Si-based Epitaxy on Advanced Technology FinFETs conference June 2019
LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design conference May 2010
Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies conference March 2019
HBD layout isolation techniques for multiple node charge collection mitigation journal December 2005
Low Leakage Current Symmetrical Dual-k 7 nm Trigate Bulk Underlap FinFET for Ultra Low Power Applications journal January 2019
Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process journal June 2009
Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes conference March 2019
Soft error rate comparison of various hardened and non-hardened flip-flops at 28-nm node conference June 2014
Evaluation of Soft-Error Tolerance by Neutrons and Heavy Ions on Flip Flops With Guard Gates in a 65-nm Thin BOX FDSOI Process journal July 2020
Sequential Element Design With Built-In Soft Error Resilience journal December 2006
RHBD techniques for mitigating effects of single-event hits using guard-gates journal December 2005
Charge-Steering Latch Design in 16 nm FinFET Technology for Improved Soft Error Hardness journal January 2017
Angular Effects on Single-Event Mechanisms in Bulk FinFET Technologies journal January 2018
Soft Error Characterization of D-FFs at the 5-nm Bulk FinFET Technology for the Terrestrial Environment conference March 2022
Upset hardened memory design for submicron CMOS technology journal January 1996
Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing journal September 2008
Estimating Single-Event Logic Cross Sections in Advanced Technologies journal January 2017
Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST) journal December 2005
Single-Event Latchup in a 7-nm Bulk FinFET Technology journal May 2021
Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node journal October 2015
Power-Aware SE Analysis of Different FF Designs at the 14-/16-nm Bulk FinFET CMOS Technology Node journal August 2018
Scaling Trends in the Soft Error Rate of SRAMs from Planar to 5-nm FinFET conference March 2021
New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level journal December 2013

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