Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Manna, Bibhas; Saha, Arnob; Jiang, Zhouhang; Ni, Kai; Sengupta, Abhronil

doi:10.1109/ted.2024.3378223

Variation-Resilient FeFET-Based In-Memory Computing Leveraging Probabilistic Deep Learning

Journal Article · Mon Mar 25 00:00:00 EDT 2024 · IEEE Transactions on Electron Devices

DOI:https://doi.org/10.1109/ted.2024.3378223· OSTI ID:2341283

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Pennsylvania State Univ., University Park, PA (United States); Penn State
Pennsylvania State Univ., University Park, PA (United States)
University of Notre Dame, IN (United States)

Reliability issues stemming from device level nonidealities of nonvolatile emerging technologies like ferroelectric field-effect transistors (FeFETs), especially at scaled dimensions, cause substantial degradation in the accuracy of in-memory crossbar-based AI systems. Here, in this work, we present a variation-aware design technique to characterize the device level variations and to mitigate their impact on hardware accuracy employing a Bayesian neural network (BNN) approach. An effective conductance variation model is derived from the experimental measurements of cycle-to-cycle (C2C) and device-to-device (D2D) variations performed on FeFET devices fabricated using 28 nm high-k metal gate technology. The variations were found to be a function of different conductance states within the given programming range, which sharply contrasts earlier efforts where a fixed variation dispersion was considered for all conductance values. Such variation characteristics formulated for three different device sizes at different read voltages were provided as prior variation information to the BNN to yield a more exact and reliable inference. Near-ideal accuracy for shallow networks (MLP5 and LeNet models) on the MNIST dataset and limited accuracy decline by ~3.8%–16.1% for deeper AlexNet models on CIFAR10 dataset under a wide range of variations corresponding to different device sizes and read voltages, demonstrates the efficacy of our proposed device-algorithm co-design technique.

View Accepted Manuscript (DOE)

Research Organization:: Pennsylvania State Univ., University Park, PA (United States)

Sponsoring Organization:: USDOE Office of Science (SC), Basic Energy Sciences (BES)

Grant/Contract Number:: SC0021118

OSTI ID:: 2341283

Journal Information:: IEEE Transactions on Electron Devices, Journal Name: IEEE Transactions on Electron Devices Journal Issue: 5 Vol. 71; ISSN 0018-9383

Publisher:: IEEECopyright Statement

Country of Publication:: United States

Language:: English

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97 MATHEMATICS AND COMPUTING
Bayesian Neural Network (BNN)
device-algorithm co-design
ferroelectric field-effect transistor (FeFET) crossbar
in-memory computing
variation-aware design

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