Skip to main content
OSTI.GOVU.S. Department of Energy Office of Scientific and Technical Information
U.S. Department of Energy
Office of Scientific and Technical Information
 

A 0.2–2 GHz Time-Interleaved Multistage Switched-Capacitor Delay Element Achieving 2.55–448.6 ns Programmable Delay Range and 330 ns/mm2 Area Efficiency

Journal Article · · IEEE Journal of Solid-State Circuits
 [1];  [1];  [1];  [1];  [1];  [1]
  1. Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
+ Show Author Affiliations

Simulation of radar returns, full-duplex systems, and signal repeaters require hundreds of ns of programmable broadband radio frequency (RF) delay in the signal path to simulate large distances in the case of radar returns, for signal cancellation in full-duplex, and for isolation from reflections in signal repeaters. However, programmable broadband RF delay has been limited to ones of ns due to challenges in miniaturization with low loss and low power consumption. In this work, we present a 0.2–2 GHz digitally programmable RF delay element based on a time-interleaved multistage switched-capacitor (TIMS-SC) approach. The proposed approach enables hundreds of ns of broadband RF delay by employing sample time expansion in multiple stages of switched-capacitor storage elements. Further, the delay element was implemented in a 45 nm SOI CMOS process and achieves a 2.55–448.6 ns programmable delay range with < 0.12% delay variation across 1.8 GHz of bandwidth at maximum delay, 2.42 ns programmable delay steps, and 330 ns/mm 2 area efficiency. Through the proposed approach, the device shows minimal delay change across a -40 °C to 85 °C temperature range and < 0.25 dB gain variation across delay settings. The device achieves 26 dB gain, 7.4 dB noise figure, and consumes 74 mW from a 1 V supply with an active area of 1.36 mm 2.

Research Organization:
Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)
Sponsoring Organization:
USDOE Laboratory Directed Research and Development (LDRD) Program
Grant/Contract Number:
NA0003525
OSTI ID:
2311647
Report Number(s):
SAND-2023-07214J
Journal Information:
IEEE Journal of Solid-State Circuits, Vol. 58, Issue 8; ISSN 0018-9200
Publisher:
IEEECopyright Statement
Country of Publication:
United States
Language:
English

References (17)

An 800-ps Origami True-Time-Delay-Based CMOS Receiver Front End for 6.5–9-GHz Phased Arrays journal January 2020
Design of Lumped-Component Programmable Delay Elements for Ultra-Wideband Beamforming journal August 2014
A 2-GHz Bandwidth, 0.25–1.7 ns True-Time-Delay Element Using a Variable-Order All-Pass Filter Architecture in 0.13 $\mu$ m CMOS journal August 2017
Digitally Enhanced Software-Defined Radio Receiver Robust to Out-of-Band Interference journal December 2009
Gigahertz Low-Loss and High Power Handling Acoustic Delay Lines Using Thin-Film Lithium-Niobate-on-Sapphire journal July 2021
A 0.2–3-GHz N-Path True Time Delay Circuit Achieving <1% Delay Variation Over Frequency journal June 2022
A 4-Element 800MHz-BW 29mW True-Time-Delay Spatial Signal Processor Enabling Fast Beam-Training with Data Communications conference September 2021
Radar target stimulation for automotive applications journal September 2018
A C-Band Commutated-LC-Negative-R Delay Circuit with Harmonic Power Recycling Achieving 1.5-ns Delay, 1.4-GHz BW, and 6-dB IL conference June 2022
A True Time Delay-based SiGe Bi-directional T/R Chipset for Large-Scale Wideband Timed Array Antennas conference June 2018
In-Band Full-Duplex Operation in High-Speed Mobile Environments: Not So Fast! journal December 2021
Analysis and Design of N-Path True-Time-Delay Circuit journal December 2020
A 0.46-mm$ ^{2}$ 4-dB NF Unified Receiver Front-End for Full-Band Mobile TV in 65-nm CMOS journal September 2011
Jitter requirements of the sampling clock in software radio receivers journal February 2006
Compact Cascadable g m -C All-Pass True Time Delay Cell With Reduced Delay Variation Over Frequency journal March 2015
A Full-Duplex Receiver Leveraging Multiphase Switched-Capacitor-Delay Based Multi-Domain FIR Filter Cancelers conference August 2020
A 0.2-2 GHz Time-Interleaved Multi-Stage Switched-Capacitor Delay Element Achieving 448.6 ns Delay and 330 ns/mm2 Area Efficiency conference June 2022

Similar Records

Related Subjects

42 ENGINEERING
delays
clocks
switches
radio frequency
bandwidth
capacitors
repeaters
broadband
low-noise amplifier
programmable delay element
radar
self-interference cancellation
switched-capacitor
true-time delay