A General Strategy to Achieve Colossal Permittivity and Low Dielectric Loss Through Constructing Insulator/Semiconductor/Insulator Multilayer Structures
- Soochow University, College of Physics, Optoelectronics and Energy, Collaborative Innovation Center of Suzhou Nano Science and Technology, and Jiangsu Key Laboratory of Thin Films (China)
- The Hong Kong Polytechnic University, Department of Applied Physics (China)
- Australian National University, Research School of Chemistry (Australia)
In this work, we propose a route to realize high-performance colossal permittivity (CP) by creating multilayer structures of insulator/semiconductor/insulator. To prove the new concept, we made heavily reduced rutile TiO{sub 2} via annealing route in Ar/H{sub 2} atmosphere. Dielectric studies show that the maximum dielectric permittivity (~ 3.0 × 10{sup 4}) of our prepared samples is about 100 times higher than that (~ 300) of conventional TiO{sub 2}. The minimum dielectric loss is 0.03 (at 10{sup 4}–10{sup 5} Hz). Furthermore, CP is almost independent of the frequency (100–10{sup 6} Hz) and the temperature (20–350 K). We suggest that the colossal permittivity is attributed to the high carrier concentration of the inner TiO{sub 2} semiconductor, while the low dielectric loss is due to the presentation of the insulator layer on the surface of TiO{sub 2}. The method proposed here can be expanded to other material systems, such as semiconductor Si sandwiched by top and bottom insulator layers of Ga{sub 2}O{sub 3}.
- OSTI ID:
- 22809996
- Journal Information:
- Journal of Low Temperature Physics, Vol. 192, Issue 5-6; Other Information: Copyright (c) 2018 Springer Science+Business Media, LLC, part of Springer Nature; http://www.springer-ny.com; Country of input: International Atomic Energy Agency (IAEA); ISSN 0022-2291
- Country of Publication:
- United States
- Language:
- English
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