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Title: Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

Abstract

We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm bettermore » fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.« less

Authors:
;  [1]
  1. Department of Electrical Engineering, University of South Carolina, Columbia, South Carolina 29208 (United States)
Publication Date:
OSTI Identifier:
22597670
Resource Type:
Journal Article
Resource Relation:
Journal Name: Journal of Applied Physics; Journal Volume: 120; Journal Issue: 6; Other Information: (c) 2016 Author(s); Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; ANODES; BREAKDOWN; DIELECTRIC MATERIALS; DOPED MATERIALS; ELECTRIC FIELDS; ELECTRONS; EMISSION; FILMS; HYDROGEN 6; LEAKAGE CURRENT; NITROGEN IONS; RELIABILITY; SILICA; SILICON CARBIDES; SILICON OXIDES; SIMULATION; STRESSES; TEMPERATURE DEPENDENCE; THICKNESS; TIME DEPENDENCE

Citation Formats

Samanta, Piyas, E-mail: piyas@vcfw.org, and Mandal, Krishna C., E-mail: mandalk@cec.sc.edu. Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias. United States: N. p., 2016. Web. doi:10.1063/1.4960579.
Samanta, Piyas, E-mail: piyas@vcfw.org, & Mandal, Krishna C., E-mail: mandalk@cec.sc.edu. Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias. United States. doi:10.1063/1.4960579.
Samanta, Piyas, E-mail: piyas@vcfw.org, and Mandal, Krishna C., E-mail: mandalk@cec.sc.edu. 2016. "Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias". United States. doi:10.1063/1.4960579.
@article{osti_22597670,
title = {Simulation of temperature dependent dielectric breakdown in n{sup +}-polySi/SiO{sub 2}/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias},
author = {Samanta, Piyas, E-mail: piyas@vcfw.org and Mandal, Krishna C., E-mail: mandalk@cec.sc.edu},
abstractNote = {We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7–25 nm) silicon dioxide (SiO{sub 2}) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n{sup +}-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO{sub 2} conduction band. Holes were generated in the n{sup +}-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness t{sub ox} and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields E{sub ox} ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (t{sub BD}) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the t{sub BD} values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO{sub 2} was observed between 27 and 225 °C.},
doi = {10.1063/1.4960579},
journal = {Journal of Applied Physics},
number = 6,
volume = 120,
place = {United States},
year = 2016,
month = 8
}
  • Low-temperature atomic layer deposition (ALD) was employed to deposit Al{sub 2}O{sub 3} as a gate dielectric in amorphous In–Ga–Zn–O thin-film transistors fabricated at temperatures below 120 °C. The devices exhibited a negligible threshold voltage shift (ΔV{sub T}) during negative bias stress, but a more pronounced ΔV{sub T} under positive bias stress with a characteristic turnaround behavior from a positive ΔV{sub T} to a negative ΔV{sub T}. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive ΔV{sub T}, which can be fitted using the stretchedmore » exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al{sub 2}O{sub 3} is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In–Ga–Zn–O channel and induce the negative ΔV{sub T} through electron doping with power-law time dependence. A rapid partial recovery of the negative ΔV{sub T} after stress is also observed during relaxation.« less
  • The high density of defect states at the dielectric/III-N interface in GaN based metal-insulator-semiconductor structures causes tremendous threshold voltage drifts, ΔV{sub th}, under forward gate bias conditions. A comprehensive study on different dielectric materials, as well as varying dielectric thickness t{sub D} and barrier thickness t{sub B}, is performed using capacitance-voltage analysis. It is revealed that the density of trapped electrons, ΔN{sub it}, scales with the dielectric capacitance under spill-over conditions, i.e., the accumulation of a second electron channel at the dielectric/AlGaN barrier interface. Hence, the density of trapped electrons is defined by the charging of the dielectric capacitance. Themore » scaling behavior of ΔN{sub it} is explained universally by the density of accumulated electrons at the dielectric/III-N interface under spill-over conditions. We conclude that the overall density of interface defects is higher than what can be electrically measured, due to limits set by dielectric breakdown. These findings have a significant impact on the correct interpretation of threshold voltage drift data and are of relevance for the development of normally off and normally on III-N/GaN high electron mobility transistors with gate insulation.« less
  • Cu penetration into low-k dielectrics can cause serious reliability issues in on-chip interconnect systems. Using secondary ion mass spectrometry with both front-side and back-side depth profiling strategies, Cu was found to diffuse into SiCOH low-k dielectric in a Cu/SiCOH/Si capacitor during Cu deposition. After bias-temperature stressing the capacitor at 270 deg. C and 2.5 MV/cm, Cu penetrates further into SiCOH, but its distribution profile is the same as that after the same temperature annealing without electrical bias, suggesting no Cu ion drift. The implication of these findings on the Cu/low-k dielectric time-dependent dielectric breakdown modeling is discussed.
  • Abstract not provided.