Properties of slow traps of ALD Al{sub 2}O{sub 3}/GeO{sub x}/Ge nMOSFETs with plasma post oxidation
- Department of Electrical Engineering and Information Systems, The University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656, Japan and JST-CREST, K's Gobancho 6F, 7 Gobancho, Chiyoda-ku, Tokyo 102-0076 (Japan)
The realization of Ge gate stacks with a small amount of slow trap density as well as thin equivalent oxide thickness and low interface state density (D{sub it}) is a crucial issue for Ge CMOS. In this study, we examine the properties of slow traps, particularly the location of slow traps, of Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge and HfO{sub 2}/Al{sub 2}O{sub 3}/GeO{sub x}/n-Ge MOS interfaces with changing the process and structural parameters, formed by atomic layer deposition (ALD) of Al{sub 2}O{sub 3} and HfO{sub 2}/Al{sub 2}O{sub 3} combined with plasma post oxidation. It is found that the slow traps can locate in the GeO{sub x} interfacial layer, not in the ALD Al{sub 2}O{sub 3} layer. Furthermore, we study the time dependence of channel currents in the Ge n-MOSFETs with 5-nm-thick Al{sub 2}O{sub 3}/GeO{sub x}/Ge gate stacks, with changing the thickness of GeO{sub x}, in order to further clarify the position of slow traps. The time dependence of the current drift and the effective time constant of slow traps do not change among the MOSFETs with the different thickness GeO{sub x}, demonstrating that the slow traps mainly exist near the interfaces between Ge and GeO{sub x}.
- OSTI ID:
- 22594465
- Journal Information:
- Applied Physics Letters, Vol. 109, Issue 3; Other Information: (c) 2016 Author(s); Country of input: International Atomic Energy Agency (IAEA); ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
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