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Title: The fundamental downscaling limit of field effect transistors

Abstract

We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.

Authors:
;  [1]
  1. Sandia National Laboratories, Albuquerque, New Mexico 87185-1322 (United States)
Publication Date:
OSTI Identifier:
22399060
Resource Type:
Journal Article
Journal Name:
Applied Physics Letters
Additional Journal Information:
Journal Volume: 106; Journal Issue: 19; Other Information: (c) 2015 Author(s); Country of input: International Atomic Energy Agency (IAEA); Journal ID: ISSN 0003-6951
Country of Publication:
United States
Language:
English
Subject:
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; COMPUTERIZED SIMULATION; DENSITY; ERRORS; MOSFET; OPERATION; ORIENTATION; PERFORMANCE; QUANTUM MECHANICS; SILICON; TEMPERATURE RANGE 0273-0400 K

Citation Formats

Mamaluy, Denis, and Gao, Xujiao. The fundamental downscaling limit of field effect transistors. United States: N. p., 2015. Web. doi:10.1063/1.4919871.
Mamaluy, Denis, & Gao, Xujiao. The fundamental downscaling limit of field effect transistors. United States. https://doi.org/10.1063/1.4919871
Mamaluy, Denis, and Gao, Xujiao. 2015. "The fundamental downscaling limit of field effect transistors". United States. https://doi.org/10.1063/1.4919871.
@article{osti_22399060,
title = {The fundamental downscaling limit of field effect transistors},
author = {Mamaluy, Denis and Gao, Xujiao},
abstractNote = {We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.},
doi = {10.1063/1.4919871},
url = {https://www.osti.gov/biblio/22399060}, journal = {Applied Physics Letters},
issn = {0003-6951},
number = 19,
volume = 106,
place = {United States},
year = {Mon May 11 00:00:00 EDT 2015},
month = {Mon May 11 00:00:00 EDT 2015}
}

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Works referencing / citing this record:

A Comparative Study on Scaling Capabilities of Si and SiGe Nanoscale Double Gate Tunneling FETs
journal, June 2019


Room temperature single electron transistor based on a size-selected aluminium cluster
journal, January 2020


Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model
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Two-Dimensional MX2 Semiconductors for Sub-5 nm Junctionless Field Effect Transistors
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The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability
journal, June 2018