The fundamental downscaling limit of field effect transistors
Abstract
We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.
- Authors:
-
- Sandia National Laboratories, Albuquerque, New Mexico 87185-1322 (United States)
- Publication Date:
- OSTI Identifier:
- 22399060
- Resource Type:
- Journal Article
- Journal Name:
- Applied Physics Letters
- Additional Journal Information:
- Journal Volume: 106; Journal Issue: 19; Other Information: (c) 2015 Author(s); Country of input: International Atomic Energy Agency (IAEA); Journal ID: ISSN 0003-6951
- Country of Publication:
- United States
- Language:
- English
- Subject:
- 71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; COMPUTERIZED SIMULATION; DENSITY; ERRORS; MOSFET; OPERATION; ORIENTATION; PERFORMANCE; QUANTUM MECHANICS; SILICON; TEMPERATURE RANGE 0273-0400 K
Citation Formats
Mamaluy, Denis, and Gao, Xujiao. The fundamental downscaling limit of field effect transistors. United States: N. p., 2015.
Web. doi:10.1063/1.4919871.
Mamaluy, Denis, & Gao, Xujiao. The fundamental downscaling limit of field effect transistors. United States. https://doi.org/10.1063/1.4919871
Mamaluy, Denis, and Gao, Xujiao. 2015.
"The fundamental downscaling limit of field effect transistors". United States. https://doi.org/10.1063/1.4919871.
@article{osti_22399060,
title = {The fundamental downscaling limit of field effect transistors},
author = {Mamaluy, Denis and Gao, Xujiao},
abstractNote = {We predict that within next 15 years a fundamental down-scaling limit for CMOS technology and other Field-Effect Transistors (FETs) will be reached. Specifically, we show that at room temperatures all FETs, irrespective of their channel material, will start experiencing unacceptable level of thermally induced errors around 5-nm gate lengths. These findings were confirmed by performing quantum mechanical transport simulations for a variety of 6-, 5-, and 4-nm gate length Si devices, optimized to satisfy high-performance logic specifications by ITRS. Different channel materials and wafer/channel orientations have also been studied; it is found that altering channel-source-drain materials achieves only insignificant increase in switching energy, which overall cannot sufficiently delay the approaching downscaling limit. Alternative possibilities are discussed to continue the increase of logic element densities for room temperature operation below the said limit.},
doi = {10.1063/1.4919871},
url = {https://www.osti.gov/biblio/22399060},
journal = {Applied Physics Letters},
issn = {0003-6951},
number = 19,
volume = 106,
place = {United States},
year = {Mon May 11 00:00:00 EDT 2015},
month = {Mon May 11 00:00:00 EDT 2015}
}
Works referenced in this record:
A simple quantum mechanical treatment of scattering in nanoscale transistors
journal, May 2003
- Venugopal, R.; Paulsson, M.; Goasguen, S.
- Journal of Applied Physics, Vol. 93, Issue 9
Iteration scheme for the solution of the two-dimensional Schrödinger-Poisson equations in quantum structures
journal, June 1997
- Trellakis, A.; Galick, A. T.; Pacelli, A.
- Journal of Applied Physics, Vol. 81, Issue 12
Efficient self-consistent quantum transport simulator for quantum devices
journal, April 2014
- Gao, X.; Mamaluy, D.; Nielsen, E.
- Journal of Applied Physics, Vol. 115, Issue 13
Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition
journal, February 2009
- Gao-Bo, Xu; Qiu-Xia, Xu
- Chinese Physics B, Vol. 18, Issue 2
The physical limits of computing
journal, May 2002
- Frank, M. P.
- Computing in Science & Engineering, Vol. 4, Issue 3
CMOS scaling for sub-90 nm to sub-10 nm
conference, January 2004
- Iwai, H.
- . 17th International Conference on VLSI Design, 17th International Conference on VLSI Design. Proceedings.
Nanowatt logic using field-effect metal-oxide semiconductor triodes
conference, January 1963
- Wanlass, F.; Sah, C.
- 1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers
How much time does FET scaling have left?
conference, June 2014
- Mamaluy, D.; Gao, X.; Tierney, B.
- 2014 International Workshop on Computational Electronics (IWCE)
Limits to binary logic switch scaling-a gedanken model
journal, November 2003
- Zhirnov, V. V.; Cavin, R. K.; Hutchby, J. A.
- Proceedings of the IEEE, Vol. 9, Issue 11
The end of CMOS scaling
journal, January 2005
- Skotnicki, T.; Hutchby, J. A.; King, T.
- IEEE Circuits and Devices Magazine, Vol. 21, Issue 1
Atomistic Modeling of Realistically Extended Semiconductor Devices with NEMO and OMEN
journal, March 2010
- Klimeck, Gerhard; Luisier, Mathieu
- Computing in Science & Engineering, Vol. 12, Issue 2
Approaching Optimal Characteristics of 10-nm High-Performance Devices: A Quantum Transport Simulation Study of Si FinFET
journal, March 2008
- Khan, Hasanur R.; Mamaluy, Denis; Vasileska, Dragica
- IEEE Transactions on Electron Devices, Vol. 55, Issue 3
Room-Temperature Operation of Silicon Single-Electron Transistor Fabricated Using Optical Lithography
journal, January 2011
- Sun, Yongshun; Singh, Navab
- IEEE Transactions on Nanotechnology, Vol. 10, Issue 1
NEMO5: A Parallel Multiscale Nanoelectronics Modeling Tool
journal, November 2011
- Steiger, Sebastian; Povolotskyi, Michael; Park, Hong-Hyun
- IEEE Transactions on Nanotechnology, Vol. 10, Issue 6
Influence of interface roughness on quantum transport in nanoscale FinFET
journal, January 2007
- Khan, H.; Mamaluy, D.; Vasileska, D.
- Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, Vol. 25, Issue 4
Irreversibility and heat generation in the computing process
journal, January 2000
- Landauer, R.
- IBM Journal of Research and Development, Vol. 44, Issue 1.2
Irreversibility and Heat Generation in the Computing Process
journal, July 1961
- Landauer, R.
- IBM Journal of Research and Development, Vol. 5, Issue 3
Nanowatt Logic Using Field-Effect Metal-Oxide Semiconductor Triodes
book, March 1991
- Wanlass, F. M.; Sah, C. T.
- Semiconductor Devices: Pioneering Papers
Works referencing / citing this record:
A Comparative Study on Scaling Capabilities of Si and SiGe Nanoscale Double Gate Tunneling FETs
journal, June 2019
- Bentrcia, Toufik; Djeffal, Fayçal; Ferhati, Hichem
- Silicon, Vol. 12, Issue 4
Room temperature single electron transistor based on a size-selected aluminium cluster
journal, January 2020
- Zharinov, Vyacheslav S.; Picot, Thomas; Scheerder, Jeroen E.
- Nanoscale, Vol. 12, Issue 2
Channel Engineering for Nanotransistors in a Semiempirical Quantum Transport Model
journal, November 2017
- Wulf, Ulrich; Kučera, Jan; Richter, Hans
- Mathematics, Vol. 5, Issue 4
Two-Dimensional MX2 Semiconductors for Sub-5 nm Junctionless Field Effect Transistors
journal, March 2018
- Peng, Bin; Zheng, Wei; Qin, Jiantao
- Materials, Vol. 11, Issue 3
The role of the Ge mole fraction in improving the performance of a nanoscale junctionless tunneling FET: concept and scaling capability
journal, June 2018
- Ferhati, Hichem; Djeffal, Fayçal; Bentrcia, Toufik
- Beilstein Journal of Nanotechnology, Vol. 9