Synchrotron-based measurement of the impact of thermal cycling on the evolution of stresses in Cu through-silicon vias
- Semiconductor and Dimensional Metrology Division, National Institute of Standards and Technology (NIST), Gaithersburg, Maryland 20899 (United States)
- Material Science and Engineering Division, National Institute of Standards and Technology (NIST), Gaithersburg, Maryland 20899 (United States)
- Advanced Photon Source, Argonne National Laboratory, Argonne, Illinois 60439-4800 (United States)
- SEMATECH, 257 Fuller Road, Albany, New York 12203 (United States)
One of the main causes of failure during the lifetime of microelectronics devices is their exposure to fluctuating temperatures. In this work, synchrotron-based X-ray micro-diffraction is used to study the evolution of stresses in copper through-silicon via (TSV) interconnects, “as-received” and after 1000 thermal cycles. For both test conditions, significant fluctuations in the measured normal and shear stresses with depth are attributed to variations in the Cu grain orientation. Nevertheless, the mean hydrostatic stresses in the “as-received” Cu TSV were very low, at (16 ± 44) MPa, most likely due to room temperature stress relaxation. In contrast, the mean hydrostatic stresses along the entire length of the Cu TSV that had undergone 1000 thermal cycles (123 ± 37) MPa were found to be eight times greater, which was attributed to increased strain-hardening. The evolution in stresses with thermal cycling is a clear indication that the impact of Cu TSVs on front-end-of-line (FEOL) device performance will change through the lifetime of the 3D stacked dies, and ought to be accounted for during FEOL keep-out-zone design rules development.
- OSTI ID:
- 22304044
- Journal Information:
- Journal of Applied Physics, Vol. 115, Issue 24; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); ISSN 0021-8979
- Country of Publication:
- United States
- Language:
- English
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