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Title: L{sub g} = 100 nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer

Abstract

In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In{sub 0.53}Ga{sub 0.47}As MOS capacitors with BeO and Al{sub 2}O{sub 3} and compared their electrical characteristics. As interface passivation layer, BeO/HfO{sub 2} bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In{sub 0.7}Ga{sub 0.3}As QW MOSFETs with a BeO/HfO{sub 2} dielectric, showing a sub-threshold slope of 100 mV/dec, and a transconductance (g{sub m,max}) of 1.1 mS/μm, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7 nm technology node and/or beyond.

Authors:
 [1]; ; ;  [2];  [2];  [3];  [4];  [5];  [6]
  1. Department of Electronics Engineering, Chungnam National University, Daejeon 305-764 (Korea, Republic of)
  2. SEMATECH, Inc., Albany, New York 12203 (United States)
  3. Department of Chemistry and Biochemistry, Texas State University, San Marcos, Texas, 78666 (United States)
  4. Department of Chemistry and Biochemistry, The University of Texas at Austin, Austin, Texas 78712 (United States)
  5. GLOBALFOUNDRIES, Santa Clara, California 95054 (United States)
  6. Department of Electrical and Computer Engineering, Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States)
Publication Date:
OSTI Identifier:
22262571
Resource Type:
Journal Article
Journal Name:
Applied Physics Letters
Additional Journal Information:
Journal Volume: 104; Journal Issue: 16; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); Journal ID: ISSN 0003-6951
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; ALUMINIUM OXIDES; BERYLLIUM OXIDES; DIELECTRIC MATERIALS; HAFNIUM OXIDES; LEAKAGE CURRENT; MOSFET; PASSIVATION; QUANTUM WELLS; SEMICONDUCTOR MATERIALS

Citation Formats

Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org, SEMATECH, Inc., Albany, New York 12203, Kwon, H. M., Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org, Veksler, D., Gilmer, D., Kirsch, P. D., Kim, D. -H., GLOBALFOUNDRIES, Malta, New York 12020, Hudnall, Todd W., Bielawski, Christopher W., Maszara, W., and Banerjee, S. K. L{sub g} = 100 nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer. United States: N. p., 2014. Web. doi:10.1063/1.4871504.
Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org, SEMATECH, Inc., Albany, New York 12203, Kwon, H. M., Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org, Veksler, D., Gilmer, D., Kirsch, P. D., Kim, D. -H., GLOBALFOUNDRIES, Malta, New York 12020, Hudnall, Todd W., Bielawski, Christopher W., Maszara, W., & Banerjee, S. K. L{sub g} = 100 nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer. United States. doi:10.1063/1.4871504.
Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org, SEMATECH, Inc., Albany, New York 12203, Kwon, H. M., Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org, Veksler, D., Gilmer, D., Kirsch, P. D., Kim, D. -H., GLOBALFOUNDRIES, Malta, New York 12020, Hudnall, Todd W., Bielawski, Christopher W., Maszara, W., and Banerjee, S. K. Mon . "L{sub g} = 100 nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer". United States. doi:10.1063/1.4871504.
@article{osti_22262571,
title = {L{sub g} = 100 nm In{sub 0.7}Ga{sub 0.3}As quantum well metal-oxide semiconductor field-effect transistors with atomic layer deposited beryllium oxide as interfacial layer},
author = {Koh, D., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org and SEMATECH, Inc., Albany, New York 12203 and Kwon, H. M. and Kim, T.-W., E-mail: dh.koh@utexas.edu, E-mail: Taewoo.Kim@sematech.org and Veksler, D. and Gilmer, D. and Kirsch, P. D. and Kim, D. -H. and GLOBALFOUNDRIES, Malta, New York 12020 and Hudnall, Todd W. and Bielawski, Christopher W. and Maszara, W. and Banerjee, S. K.},
abstractNote = {In this study, we have fabricated nanometer-scale channel length quantum-well (QW) metal-oxide-semiconductor field effect transistors (MOSFETs) incorporating beryllium oxide (BeO) as an interfacial layer. BeO has high thermal stability, excellent electrical insulating characteristics, and a large band-gap, which make it an attractive candidate for use as a gate dielectric in making MOSFETs. BeO can also act as a good diffusion barrier to oxygen owing to its small atomic bonding length. In this work, we have fabricated In{sub 0.53}Ga{sub 0.47}As MOS capacitors with BeO and Al{sub 2}O{sub 3} and compared their electrical characteristics. As interface passivation layer, BeO/HfO{sub 2} bilayer gate stack presented effective oxide thickness less 1 nm. Furthermore, we have demonstrated In{sub 0.7}Ga{sub 0.3}As QW MOSFETs with a BeO/HfO{sub 2} dielectric, showing a sub-threshold slope of 100 mV/dec, and a transconductance (g{sub m,max}) of 1.1 mS/μm, while displaying low values of gate leakage current. These results highlight the potential of atomic layer deposited BeO for use as a gate dielectric or interface passivation layer for III–V MOSFETs at the 7 nm technology node and/or beyond.},
doi = {10.1063/1.4871504},
journal = {Applied Physics Letters},
issn = {0003-6951},
number = 16,
volume = 104,
place = {United States},
year = {2014},
month = {4}
}