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Title: Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles

Abstract

In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attained with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.

Authors:
; ;  [1]
  1. Department of Electrical and Computer Engineering, University of Missouri, 349 Engineering Building West, Columbia, Missouri 65211 (United States)
Publication Date:
OSTI Identifier:
22261596
Resource Type:
Journal Article
Journal Name:
Applied Physics Letters
Additional Journal Information:
Journal Volume: 104; Journal Issue: 14; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA); Journal ID: ISSN 0003-6951
Country of Publication:
United States
Language:
English
Subject:
36 MATERIALS SCIENCE; ALUMINIUM OXIDES; CAPACITORS; LAYERS; MEMORY DEVICES; NANOSTRUCTURES; PARTICLES; PLATINUM; SEMICONDUCTOR MATERIALS; TUNNEL EFFECT

Citation Formats

Ramalingam, Balavinayagam, Zheng, Haisheng, and Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu. Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles. United States: N. p., 2014. Web. doi:10.1063/1.4870765.
Ramalingam, Balavinayagam, Zheng, Haisheng, & Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu. Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles. United States. doi:10.1063/1.4870765.
Ramalingam, Balavinayagam, Zheng, Haisheng, and Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu. Mon . "Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles". United States. doi:10.1063/1.4870765.
@article{osti_22261596,
title = {Layer-by-layer charging in non-volatile memory devices using embedded sub-2 nm platinum nanoparticles},
author = {Ramalingam, Balavinayagam and Zheng, Haisheng and Gangopadhyay, Shubhra, E-mail: gangopadhyays@missouri.edu},
abstractNote = {In this work, we demonstrate multi-level operation of a non-volatile memory metal oxide semiconductor capacitor by controlled layer-by-layer charging of platinum nanoparticle (PtNP) floating gate devices with defined gate voltage bias ranges. The device consists of two layers of ultra-fine, sub-2 nm PtNPs integrated between Al{sub 2}O{sub 3} tunneling and separation layers. PtNP size and interparticle distance were varied to control the particle self-capacitance and associated Coulomb charging energy. Likewise, the tunneling layer thicknesses were also varied to control electron tunneling to the first and second PtNP layers. The final device configuration with optimal charging behavior and multi-level programming was attained with a 3 nm Al{sub 2}O{sub 3} initial tunneling layer, initial PtNP layer with particle size 0.54 ± 0.12 nm and interparticle distance 4.65 ± 2.09 nm, 3 nm Al{sub 2}O{sub 3} layer to separate the PtNP layers, and second particle layer with 1.11 ± 0.28 nm PtNP size and interparticle distance 2.75 ± 1.05 nm. In this device, the memory window of the first PtNP layer saturated over a programming bias range of 7 V to 14 V, after which the second PtNP layer starts charging, exhibiting a multi-step memory window with layer-by-layer charging.},
doi = {10.1063/1.4870765},
journal = {Applied Physics Letters},
issn = {0003-6951},
number = 14,
volume = 104,
place = {United States},
year = {2014},
month = {4}
}