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Title: Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons

Abstract

This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate that—by changing the quiescent bias point from the off-state to the semi-on state—it is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.

Authors:
; ; ;  [1]; ; ; ; ;  [2]
  1. Department of Information Engineering, University of Padova, via Gradenigo 6/B, 35131 Padova (Italy)
  2. IMEC, Kapeldreef 75, 3001 Heverlee (Belgium)
Publication Date:
OSTI Identifier:
22261586
Resource Type:
Journal Article
Resource Relation:
Journal Name: Applied Physics Letters; Journal Volume: 104; Journal Issue: 14; Other Information: (c) 2014 AIP Publishing LLC; Country of input: International Atomic Energy Agency (IAEA)
Country of Publication:
United States
Language:
English
Subject:
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSICS; ACTIVATION ENERGY; CROSS SECTIONS; ELECTRON MOBILITY; ELECTRONS; GALLIUM NITRIDES; SEMICONDUCTOR MATERIALS; TRANSISTORS

Citation Formats

Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it, Bisi, D., Meneghesso, G., Zanoni, E., Marcon, D., Stoffels, S., Van Hove, M., Wu, T.-L., and Decoutere, S. Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons. United States: N. p., 2014. Web. doi:10.1063/1.4869680.
Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it, Bisi, D., Meneghesso, G., Zanoni, E., Marcon, D., Stoffels, S., Van Hove, M., Wu, T.-L., & Decoutere, S. Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons. United States. doi:10.1063/1.4869680.
Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it, Bisi, D., Meneghesso, G., Zanoni, E., Marcon, D., Stoffels, S., Van Hove, M., Wu, T.-L., and Decoutere, S. 2014. "Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons". United States. doi:10.1063/1.4869680.
@article{osti_22261586,
title = {Trapping in GaN-based metal-insulator-semiconductor transistors: Role of high drain bias and hot electrons},
author = {Meneghini, M., E-mail: matteo.meneghini@dei.unipd.it and Bisi, D. and Meneghesso, G. and Zanoni, E. and Marcon, D. and Stoffels, S. and Van Hove, M. and Wu, T.-L. and Decoutere, S.},
abstractNote = {This paper describes an extensive analysis of the role of off-state and semi-on state bias in inducing the trapping in GaN-based power High Electron Mobility Transistors. The study is based on combined pulsed characterization and on-resistance transient measurements. We demonstrate that—by changing the quiescent bias point from the off-state to the semi-on state—it is possible to separately analyze two relevant trapping mechanisms: (i) the trapping of electrons in the gate-drain access region, activated by the exposure to high drain bias in the off-state; (ii) the trapping of hot-electrons within the AlGaN barrier or the gate insulator, which occurs when the devices are operated in the semi-on state. The dependence of these two mechanisms on the bias conditions and on temperature, and the properties (activation energy and cross section) of the related traps are described in the text.},
doi = {10.1063/1.4869680},
journal = {Applied Physics Letters},
number = 14,
volume = 104,
place = {United States},
year = 2014,
month = 4
}
  • Effects of residual C impurities and Ga vacancies on the dynamic instabilities of AlN/AlGaN/GaN metal insulator semiconductor high electron mobility transistors are investigated. Secondary ion mass spectroscopy, positron annihilation spectroscopy, and steady state and time-resolved photoluminescence (PL) measurements have been performed in conjunction with electrical characterization and current transient analyses. The correlation between yellow luminescence (YL), C- and Ga vacancy concentrations is investigated. Time-resolved PL indicating the C{sub N} O{sub N} complex as the main source of the YL, while Ga vacancies or related complexes with C seem not to play a major role. The device dynamic performance is foundmore » to be significantly dependent on the C concentration close to the channel of the transistor. Additionally, the magnitude of the YL is found to be in agreement with the threshold voltage shift and with the on-resistance degradation. Trap analysis of the GaN buffer shows an apparent activation energy of ∼0.8 eV for all samples, pointing to a common dominating trapping process and that the growth parameters affect solely the density of trap centres. It is inferred that the trapping process is likely to be directly related to C based defects.« less
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  • We have fabricated 3 [mu]m gate length self-aligned, depletion mode GaAs metal insulator semiconductor field effect transistors exhibiting transconductances, typically in the vicinity of 160 mS/mm. This achievement is attributed to the use of Si[sub 3]N[sub 4] as the gate dielectric with a few monolayers of a Si/Ge interface layer between the GaAs channel layer and the insulator. The Si[sub 3]N[sub 4]/Si/Ge insulator structure is grown [ital in] [ital situ] using a plasma-enhanced chemical vapor deposition system which is connected by an ultrahigh vacuum transfer tube to an adjacent III-V molecular beam epitaxy system. Nearly ideal capacitance-voltage curves (compared tomore » previous publications) suggest the existence of a high quality insulator/semiconductor interface. The lowest interface trap density that has been measured, as determined from the magnitude of the conductance peak is [similar to]2[times]10[sup 11] eV[sup [minus]1] cm[sup [minus]2].« less
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