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Title: Electronic states at the interface between indium tin oxide and silicon

Abstract

Electronic properties and thermal stability of interfacial states between indium tin oxide (ITO) and monocrystalline silicon (Si) have been investigated. ITO films with thicknesses of about 300 nm were deposited by dc magnetron sputtering on n- and p-type (100) Si at room temperature. The samples were then annealed for 30 min at different temperatures in the range 100-600 deg. C, and the ITO-Si junction was found to exhibit rectifying behavior. Current-voltage (IV), capacitance-voltage (CV), and deep-level transient spectroscopy (DLTS) measurements have been used to electrically characterize the ITO-Si interface. DLTS measurements on p-type Si samples reveal a dominant hole trap at around 0.37 eV above the valence band edge. In the n-type samples, a broad band of electron traps occur in the range 0.1-0.2 eV below the conduction band edge. These electron traps display wide DLTS peaks, indicating a band of electronic energy levels rather than well-defined states originating from isolated point defects. All the traps in both the p- and n-type samples are found to be located near the ITO-Si interface. Investigations of the thermal stability of the observed electronic states show that the dominant hole trap anneal out after 30 min at 250 deg. C, while the dominantmore » electron traps can be stable up to 500 deg. C. IV and DLTS measurements demonstrate a clear correlation between the annealing of the dominant electronic states and increase in the junction rectification.« less

Authors:
; ; ;  [1]
  1. University of Oslo, Physics Department/Center for Materials Science and Nanotechnology, P.O. Box 1048, Blindern, Oslo N-0316 (Norway)
Publication Date:
OSTI Identifier:
22036740
Resource Type:
Journal Article
Journal Name:
Journal of Applied Physics
Additional Journal Information:
Journal Volume: 110; Journal Issue: 7; Other Information: (c) 2011 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); Journal ID: ISSN 0021-8979
Country of Publication:
United States
Language:
English
Subject:
75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND SUPERFLUIDITY; 36 MATERIALS SCIENCE; ANNEALING; CAPACITANCE; DEEP LEVEL TRANSIENT SPECTROSCOPY; DEPOSITION; ELECTRIC CONDUCTIVITY; ELECTRON CORRELATION; ENERGY LEVELS; EV RANGE; HOLES; INDIUM COMPOUNDS; INTERFACES; POINT DEFECTS; SEMICONDUCTOR JUNCTIONS; SEMICONDUCTOR MATERIALS; SILICON; SPUTTERING; THIN FILMS; TIN OXIDES; TRAPS; VALENCE

Citation Formats

Malmbekk, H., Vines, L., Monakhov, E. V., and Svensson, B. G. Electronic states at the interface between indium tin oxide and silicon. United States: N. p., 2011. Web. doi:10.1063/1.3643002.
Malmbekk, H., Vines, L., Monakhov, E. V., & Svensson, B. G. Electronic states at the interface between indium tin oxide and silicon. United States. doi:10.1063/1.3643002.
Malmbekk, H., Vines, L., Monakhov, E. V., and Svensson, B. G. Sat . "Electronic states at the interface between indium tin oxide and silicon". United States. doi:10.1063/1.3643002.
@article{osti_22036740,
title = {Electronic states at the interface between indium tin oxide and silicon},
author = {Malmbekk, H. and Vines, L. and Monakhov, E. V. and Svensson, B. G.},
abstractNote = {Electronic properties and thermal stability of interfacial states between indium tin oxide (ITO) and monocrystalline silicon (Si) have been investigated. ITO films with thicknesses of about 300 nm were deposited by dc magnetron sputtering on n- and p-type (100) Si at room temperature. The samples were then annealed for 30 min at different temperatures in the range 100-600 deg. C, and the ITO-Si junction was found to exhibit rectifying behavior. Current-voltage (IV), capacitance-voltage (CV), and deep-level transient spectroscopy (DLTS) measurements have been used to electrically characterize the ITO-Si interface. DLTS measurements on p-type Si samples reveal a dominant hole trap at around 0.37 eV above the valence band edge. In the n-type samples, a broad band of electron traps occur in the range 0.1-0.2 eV below the conduction band edge. These electron traps display wide DLTS peaks, indicating a band of electronic energy levels rather than well-defined states originating from isolated point defects. All the traps in both the p- and n-type samples are found to be located near the ITO-Si interface. Investigations of the thermal stability of the observed electronic states show that the dominant hole trap anneal out after 30 min at 250 deg. C, while the dominant electron traps can be stable up to 500 deg. C. IV and DLTS measurements demonstrate a clear correlation between the annealing of the dominant electronic states and increase in the junction rectification.},
doi = {10.1063/1.3643002},
journal = {Journal of Applied Physics},
issn = {0021-8979},
number = 7,
volume = 110,
place = {United States},
year = {2011},
month = {10}
}