Stress-induced Effects Caused by 3D IC TSV Packaging in Advanced Semiconductor Device Performance

Journal Article · Thu Nov 10 00:00:00 EST 2011 · AIP Conference Proceedings

DOI:https://doi.org/10.1063/1.3657899· OSTI ID:21612176

Sukharev, V; Kteyan, A; Choy, J -H; Hovsepyan, H; Markosian, A ^[1]; Zschech, E; Huebner, R ^[2]

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1. Mentor Graphics Corporation, 46871 Bayside Parkway, Fremont, CA 94538 (United States)
2. Fraunhofer Institute for Non-Destructive Testing, Maria-Reiche-Strasse 2, 01109 Dresden (Germany)

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D through-silicon-via (TSV) based technologies are outlined. The paper addresses the growing need in a simulation-based design verification flow capable to analyze a design of 3D IC stacks and to determine across-die out-of-spec variations in device electrical characteristics caused by the layout and through-silicon-via (TSV)/package-induced mechanical stress. The limited characterization/measurement capabilities for 3D IC stacks and a strict ''good die'' requirement make this type of analysis critical for the achievement of an acceptable level of functional and parametric yield and reliability. The paper focuses on the development of a design-for-manufacturability (DFM) type of methodology for managing mechanical stresses during a sequence of designs of 3D TSV-based dies, stacks and packages. A set of physics-based compact models for a multi-scale simulation to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D TSV technology is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. A strategy for generation of a simulation feeding data and respective materials characterization approach are proposed, with the goal to generate a database for multi-scale material parameters of wafer-level and package-level structures. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far.

• OSTI ID: 21612176
• Journal Information: AIP Conference Proceedings, Vol. 1395, Issue 1; Conference: Conference on frontiers of characterization and metrology for nanoelectronics 2011, Grenoble (France), 23-26 May 2011; Other Information: DOI: 10.1063/1.3657899; (c) 2011 American Institute of Physics; Country of input: International Atomic Energy Agency (IAEA); ISSN 0094-243X
• Country of Publication: United States
• Language: English

Related Subjects

36 MATERIALS SCIENCE
CALIBRATION
COMPUTERIZED SIMULATION
DESIGN
FIELD EFFECT TRANSISTORS
FINITE DIFFERENCE METHOD
FINITE ELEMENT METHOD
LAYERS
PACKAGING
PERFORMANCE
RESOLUTION
SEMICONDUCTOR MATERIALS
SILICON
STRAINS
STRESSES
TRANSMISSION ELECTRON MICROSCOPY
VALIDATION
CALCULATION METHODS
ELECTRON MICROSCOPY
ELEMENTS
ITERATIVE METHODS
MATERIALS
MATHEMATICAL SOLUTIONS
MICROSCOPY
NUMERICAL SOLUTION
SEMICONDUCTOR DEVICES
SEMIMETALS
SIMULATION
TESTING
TRANSISTORS