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Title: Formation of Ultra-Shallow Junctions by Advanced Plasma Doping Techniques

Journal Article · · AIP Conference Proceedings
DOI:https://doi.org/10.1063/1.3548332· OSTI ID:21510094
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  1. Varian Semiconductor Equipment Associates, 35 Dory Road, Gloucester, MA, 01930 (United States)

The fabrication of advanced CMOS devices calls for production worthy doping solutions to address requirements for increasingly shallow and abrupt junctions, while maintaining high dopant activation to meet series resistance requirements. Plasma Doping (PLAD), which has already been adopted in high volume manufacturing in the ultra high dose, low energy regime for advanced DRAM technology nodes, is now being investigated for source drain extension (SDE) implants, where precise and repeatable dopant placement is critical for maintaining control over device parameters. In this article, we investigate the process performance of SDE implants carried out in a VIISta registered PLAD system using p- type dopant precursors. Key metrics, such as junction depth, profile abruptness and sheet resistance are reported for as-implanted junctions, as well as samples processed with low thermal budget anneal techniques. Device performance data demonstrating the feasibility of the approach are presented. The advanced control features in the PLAD system are critical in enabling the process performance required for SDE implants.

OSTI ID:
21510094
Journal Information:
AIP Conference Proceedings, Vol. 1321, Issue 1; Conference: IIT 2010: 18. international conference on ion implantation technology, Kyoto (Japan), 6-11 Jun 2010; Other Information: DOI: 10.1063/1.3548332; (c) 2010 American Institute of Physics; ISSN 0094-243X
Country of Publication:
United States
Language:
English